Jaydeep Prakash Marathe

Works (3)

Updated: July 5th, 2023 15:55

2010 article

Feedback-directed page placement for ccNUMA via hardware-generated memory traces

Marathe, J., Thakkar, V., & Mueller, F. (2010, September 4). Journal of Parallel and Distributed Computing.

By: J. Marathe n, V. Thakkar n & F. Mueller n

author keywords: Hardware performance monitoring; NUMA; Trace guided optimization; Page placement
topics (OpenAlex): Parallel Computing and Optimization Techniques; Advanced Data Storage Technologies; Cloud Computing and Resource Management
TL;DR: Experiments show that this method, although based on lossy tracing, can efficiently and effectively improve page placement, leading to an average wall-clock execution time saving of over 20% for the tested benchmarks. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

2007 article

METRIC

Marathe, J., Mueller, F., Mohan, T., Mckee, S. A., Supinski, B. R. D., & Yoo, A. (2007, April 1). ACM Transactions on Programming Languages and Systems.

By: J. Marathe n, F. Mueller n, T. Mohan*, S. Mckee *, B. Supinski * & A. Yoo*

author keywords: algorithms; languages; performance; dynamic binary rewriting; program instrumentation; data trace generation; data trace compression; cache analysis
topics (OpenAlex): Parallel Computing and Optimization Techniques; Advanced Data Storage Technologies; Ferroelectric and Negative Capacitance Devices
TL;DR: This work presents METRIC, a software framework for isolating and understanding memory access bottlenecks using partial access traces, and demonstrates how this information can be used to isolate and understand memory access inefficiencies. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

2007 article

Source-Code-Correlated Cache Coherence Characterization of OpenMP Benchmarks

Marathe, J., & Mueller, F. (2007, May 24). IEEE Transactions on Parallel and Distributed Systems.

By: J. Marathe n & F. Mueller n

author keywords: cache memories; simulation; dynamic binary rewriting; program instrumentation; SMPs; coherence protocols
topics (OpenAlex): Parallel Computing and Optimization Techniques; Advanced Data Storage Technologies; Advanced Memory and Neural Computing
TL;DR: This paper develops a coherence analysis framework based on incremental coherence simulation of actual reference traces, and shows that cache coherence traffic can be simulated with a considerable degree of accuracy for SPMD programs, as the invalidation traffic closely matches the corresponding hardware performance counters. (via Semantic Scholar)
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Source: Web Of Science
Added: August 6, 2018

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