Works (109)
Updated: July 1st, 2024 05:05
2024 article
Nanopore Decoding with Speed and Versatility for Data Storage
Volkel, K. D., Hook, P. W., Keung, A., Timp, W., & Tuck, J. M. (2024, June 18).
doi.org (repository)
Source: ORCID
Added: June 22, 2024
2023 journal article
FrameD: framework for DNA-based data storage design, verification, and validation
BIOINFORMATICS, 39(10).
Ed(s): J. Kelso
TL;DR:
FrameD fills a void in the tools publicly available to the DNA storage community by providing a modular and extensible framework with support for massive parallelism that will help accelerate the design process of future DNA-based storage systems.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure
(OpenAlex)
Sources: ORCID, Web Of Science, NC State University Libraries
Added: October 11, 2023
2023 article
PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback
(J. Tuck & G. Byrd, Eds.). 2023 32ND INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT, pp. 74–85.
Contributors: H. Elnawawy n
Ed(s): n & G. Byrd n
author keywords: Non-Volatile Memory; Cache Architecture
TL;DR:
This work proposes PreFlush, a lightweight and transparent hardware mechanism that predicts when a cache line flush or write back is needed and speculatively performs the operation early and can improve performance by up to 25% for the WHISPER NVM benchmark suite and loop-based matrix microbenchmarks.
(via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries, ORCID
Added: February 1, 2024
2023 article
Thoth: Bridging the Gap Between Persistently Secure Memories and Memory Interfaces of Emerging NVMs
2023 IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, HPCA, pp. 94–107.
author keywords: Persistent Memory; Security Metadata; Secure NVM
TL;DR:
A novel solution is proposed, Thoth, which leverages a novel off-chip persistent partial updates combine buffer that can ensure crash consistency at the cost of a fraction of the write amplification by the state-of-the-art solutions when adapted to future interfaces.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
11. Sustainable Cities and Communities
(Web of Science)
Sources: Web Of Science, NC State University Libraries
Added: June 5, 2023
2022 journal article
DINOS: Data INspired Oligo Synthesis for DNA Data Storage
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 18(3).
author keywords: DNA information storage; DNA synthesis; DNA assembly algorithms
TL;DR:
The approach offers greater density by up to 80% over a prior general purpose gene assembly technique, and in an analysis of synthesis costs, it is estimated that DINOS is as 105× cheaper than de novo synthesis.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
Sources: ORCID, Web Of Science, NC State University Libraries
Added: April 14, 2022
2022 article
Horus: Persistent Security for Extended Persistence-Domain Memory Systems
2022 55TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), pp. 1255–1269.
author keywords: Non-Volatile Memory; eADR; secure memory
TL;DR:
Horus, a novel EPD-aware secure memory implementation that reduces the overhead during draining period of EPD system by reducing memory accesses of secure metadata and shows that Horus reduces the draining time by 5x, compared with the naive baseline design.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
11. Sustainable Cities and Communities
(Web of Science)
Sources: Web Of Science, NC State University Libraries
Added: December 12, 2022
2021 article
BBB: Simplifying Persistent Programming using Battery-Backed Buffers
2021 27TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA 2021), pp. 111–124.
TL;DR:
BBB simplifies persistent programming as the programmer does not need to insert persist barriers or flushes, and achieves nearly identical results to eADR in terms of performance and number of NVMM writes, while requiring two orders of magnitude smaller energy and time to drain.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
11. Sustainable Cities and Communities
(Web of Science)
Sources: Web Of Science, NC State University Libraries
Added: July 26, 2021
2021 review
DNA stability: a central design consideration for DNA data storage systems
[Review of ]. NATURE COMMUNICATIONS, 12(1).
MeSH headings : DNA / genetics; Data Systems; Information Storage and Retrieval
TL;DR:
It is proposed that the stability of DNA should be a key consideration in how it is used for data storage and pose specific design configurations and scenarios for future systems that best leverage the considerable advantages of DNA storage.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
7. Affordable and Clean Energy
(OpenAlex)
Sources: Web Of Science, ORCID, NC State University Libraries
Added: April 19, 2021
2021 conference paper
Dolos: Improving the Performance of Persistent Applications in ADR-Supported Secure Memory
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture.
TL;DR:
Dolos is proposed, an architecture that prioritizes persisting data without sacrificing security in order to gain a significant performance boost for persistent applications and achieves this goal by an additional minor security unit, Mi-SU, that utilizes a much faster secure process that protects only the WPQ.
(via Semantic Scholar)
Source: ORCID
Added: December 23, 2021
2021 journal article
Promiscuous molecules for smarter file operations in DNA-based data storage
NATURE COMMUNICATIONS, 12(1).
MeSH headings : Computer Simulation; DNA / chemistry; DNA Primers / chemistry; Databases, Nucleic Acid; High-Throughput Nucleotide Sequencing; Image Processing, Computer-Assisted / methods; Information Storage and Retrieval / methods; Real-Time Polymerase Chain Reaction / methods; Software; Temperature; Thermodynamics
TL;DR:
The authors leverage thermodynamics to control the access of different subsets of data in a file and provide an argument for the substantial and practical economic benefit of this generalizable strategy to organize data.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
Sources: Web Of Science, ORCID, NC State University Libraries
Added: July 12, 2021
2020 journal article
Dynamic and scalable DNA-based information storage
NATURE COMMUNICATIONS, 11(1).
MeSH headings : Algorithms; Bacteriophage T7 / genetics; DNA / genetics; DNA, Single-Stranded / genetics; Gene Expression Regulation, Viral; Genetic Code; Models, Genetic; Promoter Regions, Genetic / genetics; Transcription, Genetic
TL;DR:
It is shown that a simple architecture comprised of a T7 promoter and a single-stranded overhang domain (ss-dsDNA), can unlock dynamic DNA-based information storage with powerful capabilities and advantages.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
Sources: Web Of Science, ORCID, NC State University Libraries
Added: July 13, 2020
2020 article
Methods of crash recovery for data stored in non-volatile main memory
Solihin, Y., Alshboul, M., & Tuck, J. (2020, March).
Source: ORCID
Added: August 18, 2021
2020 journal article
Persistent Data Retention Models
ArXiv Preprint ArXiv:2009.14705.
Source: ORCID
Added: August 18, 2021
2020 journal article
The Case for Domain-Specialized Branch Predictors for Graph-Processing
IEEE COMPUTER ARCHITECTURE LETTERS, 19(2), 101–104.
author keywords: Graph-processing; branch prediction
TL;DR:
This article conducts a detailed simulation of graph-processing workloads in the GAPBS benchmark suite and shows that branch mispredictions occur frequently and are still a large limitation on performance in key graph- processing applications.
(via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: August 10, 2020
2020 conference paper
WET: write efficient loop tiling for non-volatile main memory
2020 57th ACM/IEEE Design Automation Conference (DAC), 1–6.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2019 journal article
Driving the Scalability of DNA-Based Information Storage Systems
ACS SYNTHETIC BIOLOGY, 8(6), 1241–1248.
author keywords: synthetic biology; DNA storage; information storage; nested architecture; file access; DNA sequencing
MeSH headings : DNA / chemistry; DNA / genetics; Databases, Nucleic Acid; High-Throughput Nucleotide Sequencing; Information Storage and Retrieval / methods; Sequence Analysis, DNA / methods; Synthetic Biology / methods
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
Sources: Web Of Science, ORCID
Added: July 15, 2019
2019 journal article
Dynamic DNA-based information storage
BioRxiv, 836429.
Source: ORCID
Added: August 18, 2021
2019 journal article
Dynamic modelling of the iron deficiency modulated transcriptome response in Arabidopsis thaliana roots
In Silico Plants, 1(1), diz005.
Source: ORCID
Added: August 18, 2021
2019 journal article
Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2).
author keywords: Memory systems; emerging memory technologies; computer architecture
TL;DR:
A novel recompute-based failure safety approach that removes the need to keep checkpoints or logs, thus reducing execution time overheads and improving NVMM write endurance at the expense of more complex recovery.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
11. Sustainable Cities and Communities
(Web of Science)
Sources: Web Of Science, ORCID
Added: August 5, 2019
2018 article
Hardware Supported Permission Checks On Persistent Objects for Performance and Programmability
2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 466–478.
author keywords: non-volatile memory; persistent memory programming; persistent data permission check
TL;DR:
This paper identifies permission checking in hardware as a critical mechanism that must be included when translating ObjectIDs to addresses in order to simplify programming and fully benefit from hardware translation.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
11. Sustainable Cities and Communities
(Web of Science)
Source: Web Of Science
Added: March 4, 2019
2018 conference paper
Hardware supported permission checks on persistent objects for performance and programmability
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 466–478.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2018 journal article
Inter-disciplinary research challenges in computer systems for the 2020s
National Science Foundation, USA, Tech. Rep.
Source: ORCID
Added: August 18, 2021
2018 article
Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique
2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 439–451.
author keywords: Emerging Memory Technology; Memory Systems; Multi-core and Parallel Architectures
TL;DR:
This work proposes Lazy Persistency (LP), a software persistency technique that allows caches to slowly send dirty blocks to the NVMM through natural evictions, and reduces the execution time and write amplification overheads from 9% and 21% to only 1% and 3%, respectively.
(via Semantic Scholar)
Source: Web Of Science
Added: March 4, 2019
2018 conference paper
Lazy persistency: A high-performing and write-efficient software persistency technique
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 439–451.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2017 conference paper
Characterizing the impact of soft errors across microarchitectural structures and implications for predictability
2017 IEEE International Symposium on Workload Characterization (IISWC), 250–260.
Event: IEEE
TL;DR:
This study evaluates the Architectural Vulnerability Factor (AVF) of all major in-core memory structures of an out-of-order superscalar processor, and finds that DUEAVF can be predicted using a linear regression with similar accuracy as AVF estimation, however, SDCAVF could not be predicted with the same level of accuracy.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
16. Peace, Justice and Strong Institutions
(OpenAlex)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2017 conference paper
Efficient checkpointing of loop-based codes for non-volatile main memory
2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), 318–329.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2017 conference paper
Hardware supported persistent object address translation
2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 800–812.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2017 article
Hiding the Long Latency of Persist Barriers Using Speculative Execution
44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 175–186.
author keywords: Non-Volatile Main Memory; Speculative Persistence; Failure Safety
TL;DR:
This work describes how a new set of persistence instructions work and how they can be used to implement write-ahead logging based transactions and proposes a speculative persistence architecture that reduces the execution time overheads to only 3.6%.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
11. Sustainable Cities and Communities
(Web of Science)
Source: Web Of Science
Added: August 6, 2018
2017 conference paper
Hiding the long latency of persist barriers using speculative execution
Proceedings of the 44th Annual International Symposium on Computer Architecture, 175–186.
Source: ORCID
Added: August 18, 2021
2017 conference paper
Improving the effectiveness of searching for isomorphic chains in superword level parallelism
2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 718–729.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2017 conference paper
Leveraging near data processing for high-performance checkpoint/restart
Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 1–12.
Source: ORCID
Added: August 18, 2021
2017 conference paper
Proteus: A flexible and fast software supported hardware logging approach for nvm
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 178–190.
Source: ORCID
Added: August 18, 2021
2017 journal article
ReDirect: Reconfigurable Directories for Multicore Architectures
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 14(4).
author keywords: Multicore; reconfigurable
TL;DR:
This work considers the design of directory-based cache coherence in light of the dark silicon era and the need to re-purpose transistors, and points out that directories are not needed all of the time and should be off unless it is actually needed for correctness.
(via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: August 6, 2018
2016 journal article
An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 13(3).
author keywords: Architectural vulnerability factor; cross-layer reliability
TL;DR:
This work proposes a cross-layer approach for estimating the architectural vulnerability of a processor core online that works by combining information from software, compiler, and microarchitectural layers at runtime and demonstrates the effectiveness of the approach using a dynamic protection scheme that limits vulnerability to soft errors while reducing the energy consumption.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
11. Sustainable Cities and Communities
(Web of Science)
Sources: Web Of Science, ORCID
Added: August 6, 2018
2016 article
Languages and Compilers for Parallel Computing: 28th International Workshop, LCPC 2015, Raleigh, NC, USA, September 9-11, 2015, Revised Selected Papers
Springer.
Source: ORCID
Added: August 18, 2021
2016 article
Lightweight runtime checking of C programs with RTC
Milewicz, R., Vanka, R., Tuck, J., Quinlan, D., & Pirkelbauer, P. (2016, April). COMPUTER LANGUAGES SYSTEMS & STRUCTURES, Vol. 45, pp. 191–203.
author keywords: Runtime monitoring; Source code instrumentation; Static analysis; C; C plus
TL;DR:
RTC is a runtime monitoring tool that instruments unsafe code and monitors the program execution with low overhead, and handles memory violations, arithmetic underflow/overflows, and type violations.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
2016 journal article
Lightweight runtime checking of C programs with RTC
Computer Languages, Systems & Structures, 45, 191–203.
Source: ORCID
Added: August 18, 2021
2015 journal article
Clustering and Differential Alignment Algorithm: Identification of Early Stage Regulators in the Arabidopsis thaliana Iron Deficiency Response
PLOS ONE, 10(8).
Contributors: A. Koryachko n, A. Matthiadis n, D. Muhammad n, J. Foret *, S. Brady *, J. Ducoste n , n , T. Long n , C. Williams n
MeSH headings : Algorithms; Arabidopsis / genetics; Arabidopsis / metabolism; Databases, Genetic; Gene Expression Regulation, Plant; Iron Deficiencies; Sequence Alignment; Software; Transcriptome
TL;DR:
It is proposed that this tool can be used successfully for similar time course datasets to extract additional information and infer reliable regulatory connections for individual genes, and served as a proof of concept emphasizing the utility of the CDAA for identifying unknown or missing nodes in regulatory cascades.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
Sources: Web Of Science, NC State University Libraries, ORCID
Added: August 6, 2018
2015 journal article
Computational approaches to identify regulators of plant stress response using high-throughput gene expression data
Current Plant Biology, 3-4, 20–29.
Contributors: A. Koryachko n, A. Matthiadis n, J. Ducoste n , n , T. Long n & C. Williams n
author keywords: Stress response; Transcription factors; Gene regulatory networks; Algorithms; Arabidopsis thaliana
TL;DR:
This review conceptually organizes a wide variety of developed algorithms into a classification system based on desired type of output predictions to describe completed approaches in the literature, with a focus on project goals, overall path of implemented algorithms, and biological insight gained.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
Sources: Crossref, ORCID, NC State University Libraries
Added: December 14, 2019
2015 conference paper
Computing in 3D
2015 IEEE Custom Integrated Circuits Conference (CICC), 1–6.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2015 journal article
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching
IEEE TRANSACTIONS ON COMPUTERS, 64(8), 2182–2203.
author keywords: Microarchitecture; software/hardware codesign; branch prediction; predication; pre-execution; separable branches; isa extensions; instruction level parallelism
TL;DR:
It is found that a third of mispredictions-per-1K-instructions (MPKI) come from what the authors call separable branches: branches with large control-dependent regions (not suitable for if-conversion), whose backward slices do not depend on their control- dependent instructions or have only a short dependence.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
2015 article
Runtime Checking C Programs
30TH ANNUAL ACM SYMPOSIUM ON APPLIED COMPUTING, VOLS I AND II, pp. 2107–2114.
TL;DR:
RTC is a runtime monitoring tool that instruments unsafe code and monitors the program execution and finds memory bugs and arithmetic overflows and underflows, and run-time type violations.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
2015 conference paper
Runtime checking C programs
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2107–2114.
Source: ORCID
Added: August 18, 2021
2015 conference paper
Source Mark: A Source-Level Approach for Identifying Architecture and Optimization Agnostic Regions for Performance Analysis
2015 IEEE International Symposium on Workload Characterization, 160–171.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2015 article
SourceMark: A Source-Level Approach for Identifying Architecture and Optimization Agnostic Regions for Performance Analysis
2015 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION (IISWC), pp. 160–171.
TL;DR:
This work proposes a technique that identifies regions of a desired granularity for performance evaluation using a source-to-source compiler that inserts software marks into the program's source code to divide the execution into regions with a desired dynamic instruction count.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
2014 conference paper
3D-enabled customizable embedded computer (3DECC)
2014 International 3D Systems Integration Conference (3DIC), 1–3.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2014 journal article
Control-flow decoupling: An approach for timely, non-speculative branching
IEEE Transactions on Computers, 64(8), 2182–2203.
Source: ORCID
Added: August 18, 2021
2013 conference paper
Applications and design styles for 3DIC
2013 IEEE International Electron Devices Meeting, 29–24.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2013 journal article
Automatic Parallelization of Fine-Grained Metafunctions on a Chip Multiprocessor
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(4).
author keywords: Automatic parallelization; helper computing; chip multiprocessor
TL;DR:
This work considers an automatic thread extraction technique for removing metafunctions from a main application and scheduling them on helper threads, which can leverage the resources available on a CMP to reduce the latency and overhead of fine-grained checking codes.
(via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: August 6, 2018
2012 article
Control-Flow Decoupling
2012 IEEE/ACM 45TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-45), pp. 329–340.
TL;DR:
This work proposes control-flow decoupling (CFD) to eradicate mispredictions of separable branches, and considers whether CFD is a necessary catalyst for future complexity-effective large-window architectures to tolerate memory latency.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
2012 conference paper
Control-flow decoupling
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 329–340.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2012 conference paper
Efficient and accurate data dependence profiling using software signatures
Proceedings of the Tenth International Symposium on Code Generation and Optimization, 186–195.
Source: ORCID
Added: August 18, 2021
2012 journal article
Efficiently Exploiting Memory Level Parallelism on Asymmetric Coupled Cores in the Dark Silicon Era
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(4).
author keywords: Design; Performance; Memory level parallelism; multicore; asymmetric multicore processor; dark silicon
TL;DR:
This work quantifies the potential for exploiting core customization to speedup programs during regions of high MLP and proposes a hardware-level, application steering mechanism called Symbiotic Core Execution (SCE), which yields an important message for designing AMPs with specialized cores.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018
2012 conference paper
HiRe: using hint & release to improve synchronization of speculative threads
HiRe: using hint & release to improve synchronization of speculative threads. Proceedings of the 26th ACM international conference on Supercomputing, 143–152.
Source: ORCID
Added: August 18, 2021
2011 journal article
Article 28 (21 pages)-Efficiently Exploiting Memory Level Parallelism on Asymmetric Coupled Cores in the Dark Silicon Era
ACM Transactions on Architecture and Code Optimization-TACO, 8(4).
Source: ORCID
Added: August 18, 2021
2011 conference paper
AutoPipe: A Pipeline Parallelization Framework in GCC
GROW2011: International Workshop on GCC Research Opportunities.
Source: NC State University Libraries
Added: August 6, 2018
2011 conference paper
Automatic Parallelization of Fine-grained Meta-functions on a Chip Multiprocessor
International Symposium on Code Generation and Optimization, 130–140.
TL;DR:
This work considers an automatic thread extraction technique for removing meta-functions from a main application and scheduling them on helper threads, which can leverage the resources available on a CMP to reduce the latency and overhead of fine-grained checking codes.
(via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2011 conference paper
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
International symposium on high-performance computer, 99–110.
TL;DR:
A hardware-accelerated queue, or HAQu, is proposed that adds hardware to a CMP that accelerates operations on software queues, and ensures that the full state of the queue is stored in the application's address space, thereby ensuring virtualization.
(via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018
2011 conference paper
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
2011 IEEE 17th International Symposium on High Performance Computer Architecture, 99–110.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2011 journal article
SPECIAL ISSUE ON HIGH-PERFORMANCE AND EMBEDDED ARCHITECTURES AND COMPILERS
ACM Transactions On, 8(4).
Source: ORCID
Added: August 18, 2021
2010 conference paper
Design Trade-offs for Memory Level Parallelism on an Asymmetric Multicore System
Pespma 2010-Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture.
Source: ORCID
Added: August 18, 2021
2010 conference paper
Design Tradeoffs for Memory-Level Parallelism on an Asymmetric Multicore System
Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures.
Source: NC State University Libraries
Added: August 6, 2018
2010 conference paper
MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management
International Parallel and Distributed Processing Symposium.
TL;DR:
It is shown that an efficient MMT design can give significant performance improvement by extracting parallelism while being agnostic to the underlying memory management library algorithms and data structures, and how parallelism provided by MMT can be beneficial for high overhead memory management tasks.
(via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018
2010 conference paper
Mmt: Exploiting fine-grained parallelism in dynamic memory management
2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 1–12.
Event: IEEE
Source: ORCID
Added: August 18, 2021
2010 conference paper
Speculative parallelization of partial reduction variables
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization, 141–150.
TL;DR:
An algorithm that allows the compiler to detect partial reduction variables (PRV) and an implementation in a TLS system to parallelize PRVs that works by a combination of techniques at compile time and in the hardware are described.
(via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2009 conference paper
Memory management thread for heap allocation intensive sequential applications
Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture, 35–42.
TL;DR:
This paper proposes a way for exploiting multicore parallelism in dynamic memory management for sequential applications, by spinning off memory allocation and deallocation functions to a separate thread that is referred to as memory management thread (MMT).
(via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2009 journal article
SOFTSIG: SOFTWARE-EXPOSED HARDWARE SIGNATURES FOR CODE ANALYSIS AND OPTIMIZATION
IEEE MICRO, 29(1), 84–95.
Sources: Web Of Science, ORCID
Added: August 6, 2018
2009 journal article
The Bulk Multicore Architecture for Improved Programmability
COMMUNICATIONS OF THE ACM, 52(12), 58–65.
TL;DR:
Easing the programmer's burden does not compromise system performance or increase the complexity of hardware implementation.
(via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries, ORCID
Added: August 6, 2018
2008 report
A Data Dependence Profiler for the GNU Compiler Collection
In Technical Report- Not held in TRLN member libraries.
Source: NC State University Libraries
Added: August 6, 2018
2008 conference paper
Parallelizing Mudflap Using Thread-Level Speculation on a CMP
Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures.
Source: NC State University Libraries
Added: August 6, 2018
2008 conference paper
Parallelizing Mudflap using Thread-Level Speculation on a Chip Multiprocessor
Proc. of the 2008 Workshop on Parallel Execution of Sequential Programs on Multicore Architectures, 72–80.
Event: Citeseer
Source: ORCID
Added: August 18, 2021
2008 conference paper
SoftSig: Software Exposed Hardware Signatures for Code Analysis and Optimization
ACM International Symposium on Architectural Support for Programming Languages and Operating Systems, 145–156.
TL;DR:
The Memoise algorithm demonstrates SoftSig's versatility by detecting and eliminating redundant function calls.
(via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018
2008 journal article
SoftSig: software-exposed hardware signatures for code analysis and optimization
ACM SIGOPS Operating Systems Review, 42(2), 145–156.
Source: ORCID
Added: August 18, 2021
2008 article
System and method for cache coherency in a cache with different cache location lengths
(2008, November).
Source: ORCID
Added: August 18, 2021
2007 conference paper
BulkSC: Bulk enforcement of sequential consistency
Proceedings of the 34th annual international symposium on Computer architecture, 278–289.
TL;DR:
Bulk Enforcement of SC (BulkSC) is proposed, anovel way of providing SC that is simple to implement and offers performance comparable to Release Consistency (RC).
(via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2007 conference paper
CAP: Criticality analysis for power-efficient speculative multithreading
2007 25th International Conference on Computer Design, 409–416.
Event: IEEE
TL;DR:
A novel, widely-applicable task-criticality model for SM is developed and CAP, a novel architecture that builds a task- criticality graph dynamically and uses it to make scheduling decisions in a SM CMP is proposed.
(via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2007 report
Efficient support for speculative tasking
Source: ORCID
Added: August 18, 2021
2006 conference paper
Are We Ready for High Memory-Level Parallelism?
Workshop on Memory Performance Issues.
Source: NC State University Libraries
Added: August 6, 2018
2006 conference paper
Are we ready for high memorylevel parallelism?
4th Workshop on Memory Performance Issues.
Source: ORCID
Added: August 18, 2021
2006 journal article
Boosting SMT trace processors performance with data cache misssensitive thread scheduling mechanism
Microprocessors and Microsystems, 30(5), 225–233.
Source: ORCID
Added: August 18, 2021
2006 conference paper
Bulk Disambiguation of Speculative Threads in Multiprocessors
IEEE/ACM Annual International Symposium on Computer Architecture, 227–238.
Source: NC State University Libraries
Added: August 6, 2018
2006 journal article
Bulk disambiguation of speculative threads in multiprocessors
ACM SIGARCH Computer Architecture News, 34(2), 227–238.
Source: ORCID
Added: August 18, 2021
2006 journal article
CAVA: Using checkpoint-assisted value prediction to hide L2 misses
ACM Transactions on Architecture and Code Optimization (TACO), 3(2), 182–208.
TL;DR:
This work proposes hiding L2 misses with Checkpoint-Ass VAlue prediction (CAVA), a proposed scheme that uses fast checkpointing, speculative buffering, and a modest-sized value prediction structure that has about 50% accuracy.
(via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2006 journal article
Energy-Efficient Thread-Level Speculation on a CMP
IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, 80–91.
Source: NC State University Libraries
Added: August 6, 2018
2006 journal article
Energy-efficient thread-level speculation
IEEE Micro, 26(1), 80–91.
Source: ORCID
Added: August 18, 2021
2006 conference paper
POSH: a TLS compiler that exploits program structure
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, 158–167.
TL;DR:
POSH is a new, fully automated TLS compiler built on top of gcc that leverages the code structures created by the programmer, namely subroutines and loops to generate speculative tasks that are crucial to overall TLS performance.
(via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2006 conference paper
Scalable cache miss handling for high memory-level parallelism
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 409–422.
Event: IEEE
TL;DR:
This paper presents a novel scalable MHA design for high-MLP processors, which is hierarchical, with a small MSHR file per cache bank, and a larger MS HR file shared by all banks, and uses a Bloom filter to reduce searches in the largerMSHR file.
(via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2006 article
System and method for non-uniform cache in a multi-core processor
Hughes, C., Tuck, J., Lee, V., & Chen, Y.-kuang. (2006, June).
Source: ORCID
Added: August 18, 2021
2005 journal article
Languages and compilers for parallel computing
Source: ORCID
Added: August 18, 2021
2005 conference paper
POSH: A profiler-enhanced TLS compiler that leverages program structure
IBM Watson P= AC2 Conference, 83–92.
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2005 article
SESC simulator, January 2005
Source: ORCID
Added: August 18, 2021
2005 conference paper
Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation
ACM International Conference on Supercomputing, 179–188.
TL;DR:
This paper is the first to propose a set of microarchitectural mechanisms that fundamentally enable fast TLS with out-of-order spawn in a CMP, and develops a fully-automated TLS compiler for aggressive out- of- order spawn.
(via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018
2005 conference paper
Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation
Proceedings of the 19th Annual International conference on Supercomputing, 179–188.
Source: ORCID
Added: August 18, 2021
2005 conference paper
Thread-level speculation on a CMP can be energy efficient
Proceedings of the 19th annual international conference on Supercomputing, 219–228.
TL;DR:
This paper first identifies the main sources of dynamic energy consumption in TLS, then presents simple energy-saving optimizations that cut the energy cost of TLS by over 60% on average with minimal performance impact.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018
2004 journal article
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
IEEE Computer Architecture Letters, 7–10.
Source: NC State University Libraries
Added: August 6, 2018
2004 journal article
CAVA: Hiding L2 misses with checkpoint-assisted value prediction
IEEE Computer Architecture Letters, 3(1), 7–7.
Source: ORCID
Added: August 18, 2021
2003 thesis
A novel compiler framework for a chip-multiprocessor architecture with thread-level speculation
University of Illinois at Urbana-Champaign.
Source: ORCID
Added: August 18, 2021
2002 journal article
Morphable multithreaded memory tiles (M3T) architecture
University of Illinois UIUC-CS Technical Report.
Source: ORCID
Added: August 18, 2021
2002 report
Sphinx Parallelization
Source: ORCID
Added: August 18, 2021
2002 journal article
Sphinx parallelization
Dept. of Computer Science, University of Illinois, Tech. Rep. UIUCDCS.
Source: ORCID
Added: August 18, 2021
2001 journal article
Handling crosscutting constraints in domain-specific modeling
Communications of the ACM, 44(10), 87–93.
Source: ORCID
Added: August 18, 2021
2001 journal article
Handling crosscutting constraints in domain-specific modeling - Uniting AOP with model-integrated computing.
COMMUNICATIONS OF THE ACM, 44(10), 87–93.
TL;DR:
Whenever the description of a software artifact exhibits crosscutting structure, the principles of modularity espoused by AO offer a powerful technology for supporting separation of concerns, which is found to be true especially in the area of domain-specific modeling.
(via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
2001 journal article
Institute for Software Integrated Systems Vanderbilt University Nashville Tennessee 37235
ISIS, 1, 200.
Source: ORCID
Added: August 18, 2021
journal article
Abstract Parallel Operators: Revamping the Hardware/Software Interface for the Multicore Era
Patsilaras, G., Lee, S., & Tuck, J.
Source: ORCID
Added: August 18, 2021
journal article
Improving MemoiSE Using Function Splitting
Vanka, R., & Tuck, J.
Source: ORCID
Added: August 18, 2021
report
Improving MemoiSE via Function Splitting
In Technical Report- Not held in TRLN member libraries (Vol. 2009).
Source: NC State University Libraries
Added: August 6, 2018
journal article
Industry Session Program Committee
Akin, B., Baghsorkhi, S., Bai, Y., Fletcher, C., Healy, M., Huang, M., … others.
Source: ORCID
Added: August 18, 2021
journal article
Tasking with out-of-order spawn in TLS chip multiprocessors
Tuck, J., & Torrellas, J.
Source: ORCID
Added: August 18, 2021
journal article
Thread-Level Speculation on a CMP Can Be Energy Efficient
Strauss, J. R. K., Ceze, L., Liu, W., Sarangi, S., Tuck, J., & Torrellas, J.
Source: ORCID
Added: August 18, 2021
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