James Tuck

Driving the Scalability of DNA-Based Information Storage Systems

ACS SYNTHETIC BIOLOGY, 8(6), 1241–1248.

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2).

Hardware Supported Permission Checks On Persistent Objects for Performance and Programmability

In 2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA) (pp. 466–478).

Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique

In 2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA) (pp. 439–451).

Characterizing the impact of soft errors across microarchitectural structures and implications for predictability

In Proceedings of the 2017 ieee international symposium on workload characterization (iiswc) (pp. 250–260).

Hiding the long latency of persist barriers using speculative execution

In 44th Annual International Symposium on Computer Architecture (ISCA 2017) (pp. 175–186).

Redirect: Reconfigurable directories for multicore architectures

ACM Transactions on Architecture and Code Optimization, 14(4).

An accurate cross-layer approach for online architectural vulnerability estimation

ACM Transactions on Architecture and Code Optimization, 13(3).

Lightweight runtime checking of C programs with RTC

Computer Languages Systems & Structures, 45, 191–203.

Clustering and differential alignment algorithm: Identification of early stage regulators in the Arabidopsis thaliana iron deficiency response

PLoS One, 10(8).

Control-flow decoupling: An approach for timely, non-speculative branching

IEEE Transactions on Computers, 64(8), 2182–2203.

Runtime checking C programs

In 30th Annual ACM Symposium on Applied Computing, Vols I and II (pp. 2107–2114).

SourceMark: A source-level approach for identifying architecture and optimization agnostic regions for performance analysis

In 2015 IEEE International Symposium on Workload Characterization (IISWC) (pp. 160–171).

Automatic parallelization of fine-grained metafunctions on a chip multiprocessor

ACM Transactions on Architecture and Code Optimization, 10(4).

Control-flow decoupling

In 2012 ieee/acm 45th international symposium on microarchitecture (micro-45) (pp. 329–340).

Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era

ACM Transactions on Architecture and Code Optimization, 8(4).

AutoPipe: A Pipeline Parallelization Framework in GCC

In GROW2011: International Workshop on GCC Research Opportunities.

Automatic Parallelization of Fine-grained Meta-functions on a Chip Multiprocessor

In International Symposium on Code Generation and Optimization (pp. 130–140).

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

In International symposium on high-performance computer (pp. 99–110).

Design Tradeoffs for Memory-Level Parallelism on an Asymmetric Multicore System

In Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures.

MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management

In International Parallel and Distributed Processing Symposium.

Speculative parallelization of partial reduction variables

In International Symposium on Code Generation and Optimization (pp. 141–150).

Memory Management Thread for Heap Allocation Intensive Applications

In Workshop on Memory Performance: Dealing with Applications, Systems Architecture.

SOFTSIG: Software-exposed hardware signatures for code analysis and optimization

IEEE Micro, 29(1), 84–95.

The Bulk Multicore for Improved Programmability

Communications of the ACM.

A Data Dependence Profiler for the GNU Compiler Collection

Technical Report- Not held in TRLN member libraries.

Parallelizing Mudflap Using Thread-Level Speculation on a CMP

In Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures.

SoftSig: Software Exposed Hardware Signatures for Code Analysis and Optimization

In ACM International Symposium on Architectural Support for Programming Languages and Operating Systems (pp. 145–156).

BulkSC: Bulk Enforcement of Sequential Consistency

In IEEE/ACM Annual International Symposium on Computer Architecture (pp. 278–289).

CAP: Criticality Analysis for Power Efficient Speculative Multithreading on a CMP

In IEEE International Conference on Computer Design (pp. 409–416).

Are We Ready for High Memory-Level Parallelism?

In Workshop on Memory Performance Issues.

Bulk Disambiguation of Speculative Threads in Multiprocessors

In IEEE/ACM Annual International Symposium on Computer Architecture (pp. 227–238).

CAVA: Using Checkpoint Assisted Value Prediction to Hide L2 Misses

ACM Transactions on Architecture and Code Optimization, 182–208.

Energy-Efficient Thread-Level Speculation on a CMP

IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, 80–91.

POSH: A TLS Compiler that Exploits Program Structure

In ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) (pp. 158–167).

Scalable Miss Handling Architecture for High Memory-Level Parallelism

In IEEE Annual International Symposium on Microarchitecture (MICRO) (pp. 409–421).

POSH: A Pro?ler-Enhanced TLS Compiler that Leverages Program Structure

In IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P = AC2) (pp. 83–92).

Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation

In ACM International Conference on Supercomputing (pp. 179–188).

Thread- Level Speculation on a CMP Can Be Energy Efficient

In ACM International Conference on Supercomputing (pp. 219–228).

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction

IEEE Computer Architecture Letters, 7–10.

Handling Crosscutting Constraints in Domain-Speci?c Modeling

Communications of the ACM, 44(10), 87–93.

Improving MemoiSE via Function Splitting

Technical Report- Not held in TRLN member libraries (Vol. 2009).