Works (107)

Updated: November 8th, 2023 17:21

2023 journal article

FrameD: framework for DNA-based data storage design, verification, and validation

Bioinformatics.

By: K. Volkel n, K. Lin n, P. Hookโ€‰*, W. Timpโ€‰*, A. Keungโ€‰ n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ

Ed(s): J. Kelso

Source: ORCID
Added: October 11, 2023

2023 article

Thoth: Bridging the Gap Between Persistently Secure Memories and Memory Interfaces of Emerging NVMs

2023 IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, HPCA, pp. 94โ€“107.

By: X. Han n, J. Tuck nโ€‰ & A. Awad n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Persistent Memory; Security Metadata; Secure NVM
Sources: Web Of Science, ORCID
Added: June 5, 2023

2022 journal article

DINOS: Data INspired Oligo Synthesis for DNA Data Storage

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 18(3).

By: K. Volkel n, K. Tomek n, A. Keung n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: DNA information storage; DNA synthesis; DNA assembly algorithms
Sources: ORCID, Web Of Science
Added: April 14, 2022

2022 article

Horus: Persistent Security for Extended Persistence-Domain Memory Systems

2022 55TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), pp. 1255โ€“1269.

By: X. Han n, J. Tuck nโ€‰ & A. Awad n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Non-Volatile Memory; eADR; secure memory
Sources: Web Of Science, ORCID
Added: December 12, 2022

2021 article

BBB: Simplifying Persistent Programming using Battery-Backed Buffers

2021 27TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA 2021), pp. 111โ€“124.

By: M. Alshboul n, P. Ramrakhyani*, W. Wangโ€‰*, J. Tuck nโ€‰ & Y. Solihinโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: Web Of Science, ORCID
Added: July 26, 2021

2021 review

DNA stability: a central design consideration for DNA data storage systems

[Review of ]. NATURE COMMUNICATIONS, 12(1).

By: K. Matange n, J. Tuck nโ€‰ & A. Keung n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
MeSH headings : DNA / genetics; Data Systems; Information Storage and Retrieval
Sources: Web Of Science, ORCID
Added: April 19, 2021

2021 conference paper

Dolos: Improving the Performance of Persistent Applications in ADR-Supported Secure Memory

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture.

By: X. Han n, J. Tuck nโ€‰ & A. Awadโ€‰ n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: ORCID
Added: December 23, 2021

2021 journal article

Promiscuous molecules for smarter file operations in DNA-based data storage

NATURE COMMUNICATIONS, 12(1).

By: K. Tomek n, K. Volkel n, E. Indermaur n, J. Tuck nโ€‰ & A. Keung n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
MeSH headings : Computer Simulation; DNA / chemistry; DNA Primers / chemistry; Databases, Nucleic Acid; High-Throughput Nucleotide Sequencing; Image Processing, Computer-Assisted / methods; Information Storage and Retrieval / methods; Real-Time Polymerase Chain Reaction / methods; Software; Temperature; Thermodynamics
Sources: Web Of Science, ORCID
Added: July 12, 2021

2020 journal article

Dynamic and scalable DNA-based information storage

NATURE COMMUNICATIONS, 11(1).

By: K. Lin n, K. Volkel n, J. Tuck nโ€‰ & A. Keung n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
MeSH headings : Algorithms; Bacteriophage T7 / genetics; DNA / genetics; DNA, Single-Stranded / genetics; Gene Expression Regulation, Viral; Genetic Code; Models, Genetic; Promoter Regions, Genetic / genetics; Transcription, Genetic
Sources: Web Of Science, ORCID
Added: July 13, 2020

2020 article

Methods of crash recovery for data stored in non-volatile main memory

Solihin, Y., Alshboul, M., & Tuck, J. (2020, March).

By: Y. Solihin, M. Alshboul & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2020 journal article

Persistent Data Retention Models

ArXiv Preprint ArXiv:2009.14705.

By: T. Wang & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2020 journal article

The Case for Domain-Specialized Branch Predictors for Graph-Processing

IEEE COMPUTER ARCHITECTURE LETTERS, 19(2), 101โ€“104.

By: A. Samara n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Graph-processing; branch prediction
Sources: Web Of Science, ORCID
Added: August 10, 2020

2020 conference paper

WET: write efficient loop tiling for non-volatile main memory

2020 57th ACM/IEEE Design Automation Conference (DAC), 1โ€“6.

By: M. Alshboul, J. Tuckโ€‰ & Y. Solihin

Event: IEEE

Source: ORCID
Added: August 18, 2021

2019 journal article

Driving the Scalability of DNA-Based Information Storage Systems

ACS SYNTHETIC BIOLOGY, 8(6), 1241โ€“1248.

By: K. Tomek n, K. Volkel n, A. Simpson n, A. Hass n, E. Indermaur n, J. Tuck nโ€‰, A. Keung n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: synthetic biology; DNA storage; information storage; nested architecture; file access; DNA sequencing
MeSH headings : DNA / chemistry; DNA / genetics; Databases, Nucleic Acid; High-Throughput Nucleotide Sequencing; Information Storage and Retrieval / methods; Sequence Analysis, DNA / methods; Synthetic Biology / methods
Sources: Web Of Science, ORCID
Added: July 15, 2019

2019 journal article

Dynamic DNA-based information storage

BioRxiv, 836429.

By: K. Lin, A. Keung & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2019 journal article

Dynamic modelling of the iron deficiency modulated transcriptome response in Arabidopsis thaliana roots

In Silico Plants, 1(1), diz005.

By: A. Koryachko, A. Matthiadis, S. Haque, D. Muhammad, J. Ducoste, J. Tuckโ€‰, T. Long, C. Williams

Source: ORCID
Added: August 18, 2021

2019 journal article

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2).

co-author countries: Egypt ๐Ÿ‡ช๐Ÿ‡ฌ Japan ๐Ÿ‡ฏ๐Ÿ‡ต United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Memory systems; emerging memory technologies; computer architecture
Sources: Web Of Science, ORCID
Added: August 5, 2019

2018 article

Hardware Supported Permission Checks On Persistent Objects for Performance and Programmability

2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 466โ€“478.

By: T. Wangโ€‰ n, S. Sambasivam n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: non-volatile memory; persistent memory programming; persistent data permission check
Source: Web Of Science
Added: March 4, 2019

2018 conference paper

Hardware supported permission checks on persistent objects for performance and programmability

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 466โ€“478.

By: T. Wang, S. Sambasivam & J. Tuckโ€‰

Event: IEEE

Source: ORCID
Added: August 18, 2021

2018 journal article

Inter-disciplinary research challenges in computer systems for the 2020s

National Science Foundation, USA, Tech. Rep.

By: A. Cohen, X. Shen, J. Torrellas, J. Tuckโ€‰, Y. Zhou, S. Adve, I. Akturk, S. Bagchi ...

Source: ORCID
Added: August 18, 2021

2018 article

Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique

2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 439โ€“451.

By: M. Alshboul n, J. Tuck nโ€‰ & Y. Solihin n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Emerging Memory Technology; Memory Systems; Multi-core and Parallel Architectures
Source: Web Of Science
Added: March 4, 2019

2018 conference paper

Lazy persistency: A high-performing and write-efficient software persistency technique

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 439โ€“451.

By: M. Alshboul, J. Tuckโ€‰ & Y. Solihin

Event: IEEE

Source: ORCID
Added: August 18, 2021

2017 conference paper

Characterizing the impact of soft errors across microarchitectural structures and implications for predictability

2017 IEEE International Symposium on Workload Characterization (IISWC), 250โ€“260.

By: B. Wibowo n, A. Agrawal n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ

Event: IEEE

Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2017 conference paper

Efficient checkpointing of loop-based codes for non-volatile main memory

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), 318โ€“329.

By: H. Elnawawy, M. Alshboul, J. Tuckโ€‰ & Y. Solihin

Event: IEEE

Source: ORCID
Added: August 18, 2021

2017 conference paper

Hardware supported persistent object address translation

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 800โ€“812.

By: T. Wang, S. Sambasivam, Y. Solihin & J. Tuckโ€‰

Event: IEEE

Source: ORCID
Added: August 18, 2021

2017 article

Hiding the Long Latency of Persist Barriers Using Speculative Execution

44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 175โ€“186.

By: S. Shin n, J. Tuck nโ€‰ & Y. Solihin n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Non-Volatile Main Memory; Speculative Persistence; Failure Safety
Source: Web Of Science
Added: August 6, 2018

2017 conference paper

Hiding the long latency of persist barriers using speculative execution

Proceedings of the 44th Annual International Symposium on Computer Architecture, 175โ€“186.

By: S. Shin, J. Tuckโ€‰ & Y. Solihin

Source: ORCID
Added: August 18, 2021

2017 conference paper

Improving the effectiveness of searching for isomorphic chains in superword level parallelism

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 718โ€“729.

By: J. Huh & J. Tuckโ€‰

Event: IEEE

Source: ORCID
Added: August 18, 2021

2017 conference paper

Leveraging near data processing for high-performance checkpoint/restart

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 1โ€“12.

By: A. Agrawal, G. Loh & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2017 conference paper

Proteus: A flexible and fast software supported hardware logging approach for nvm

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 178โ€“190.

By: S. Shin, S. Tirukkovalluri, J. Tuckโ€‰ & Y. Solihin

Source: ORCID
Added: August 18, 2021

2017 journal article

ReDirect: Reconfigurable Directories for Multicore Architectures

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 14(4).

By: G. Patsilaras* & J. Tuck nโ€‰

co-author countries: United Kingdom of Great Britain and Northern Ireland ๐Ÿ‡ฌ๐Ÿ‡ง United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Multicore; reconfigurable
Sources: Web Of Science, ORCID
Added: August 6, 2018

2016 journal article

An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 13(3).

By: B. Wibowo n, A. Agrawal n, T. Stanton n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Architectural vulnerability factor; cross-layer reliability
Sources: Web Of Science, ORCID
Added: August 6, 2018

2016 article

Languages and Compilers for Parallel Computing: 28th International Workshop, LCPC 2015, Raleigh, NC, USA, September 9-11, 2015, Revised Selected Papers

Springer.

By: X. Shen, F. Mueller & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2016 article

Lightweight runtime checking of C programs with RTC

Milewicz, R., Vanka, R., Tuck, J., Quinlan, D., & Pirkelbauer, P. (2016, April). COMPUTER LANGUAGES SYSTEMS & STRUCTURES, Vol. 45, pp. 191โ€“203.

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Runtime monitoring; Source code instrumentation; Static analysis; C; C plus
Source: Web Of Science
Added: August 6, 2018

2016 journal article

Lightweight runtime checking of C programs with RTC

Computer Languages, Systems & Structures, 45, 191โ€“203.

By: R. Milewicz, R. Vanka, J. Tuckโ€‰, D. Quinlan & P. Pirkelbauer

Source: ORCID
Added: August 18, 2021

2015 journal article

Clustering and Differential Alignment Algorithm: Identification of Early Stage Regulators in the Arabidopsis thaliana Iron Deficiency Response

PLOS ONE, 10(8).

By: A. Koryachko n, A. Matthiadis n, D. Muhammad n, J. Foret*, S. Bradyโ€‰*, J. Ducoste nโ€‰, J. Tuck nโ€‰, T. Long nโ€‰, C. Williams nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ

Contributors: A. Koryachko n, A. Matthiadis n, D. Muhammad n, J. Foret*, S. Bradyโ€‰*, J. Ducoste nโ€‰, J. Tuck nโ€‰, T. Long nโ€‰, C. Williams nโ€‰

MeSH headings : Algorithms; Arabidopsis / genetics; Arabidopsis / metabolism; Databases, Genetic; Gene Expression Regulation, Plant; Iron Deficiencies; Sequence Alignment; Software; Transcriptome
Sources: Web Of Science, ORCID
Added: August 6, 2018

2015 journal article

Computational approaches to identify regulators of plant stress response using high-throughput gene expression data

Current Plant Biology, 3-4, 20โ€“29.

By: A. Koryachko n, A. Matthiadis n, J. Ducoste nโ€‰, J. Tuck nโ€‰, T. Long nโ€‰ & C. Williams nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ

Contributors: A. Koryachko n, A. Matthiadis n, J. Ducoste nโ€‰, J. Tuck nโ€‰, T. Long nโ€‰ & C. Williams nโ€‰

author keywords: Stress response; Transcription factors; Gene regulatory networks; Algorithms; Arabidopsis thaliana
Sources: Crossref, ORCID
Added: December 14, 2019

2015 conference paper

Computing in 3D

2015 IEEE Custom Integrated Circuits Conference (CICC), 1โ€“6.

By: P. Franzon, E. Rotenberg, J. Tuckโ€‰, W. Davis, H. Zhou, J. Schabel, Z. Zhang, J. Dwiel ...

Event: IEEE

Source: ORCID
Added: August 18, 2021

2015 journal article

Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching

IEEE TRANSACTIONS ON COMPUTERS, 64(8), 2182โ€“2203.

By: R. Sheikh*, J. Tuck nโ€‰ & E. Rotenberg n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Microarchitecture; software/hardware codesign; branch prediction; predication; pre-execution; separable branches; isa extensions; instruction level parallelism
Source: Web Of Science
Added: August 6, 2018

2015 article

Runtime Checking C Programs

30TH ANNUAL ACM SYMPOSIUM ON APPLIED COMPUTING, VOLS I AND II, pp. 2107โ€“2114.

By: R. Milewiczโ€‰*, R. Vanka*, J. Tuck nโ€‰, D. Quinlanโ€‰* & P. Pirkelbauerโ€‰*

co-author countries: Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: Web Of Science
Added: August 6, 2018

2015 conference paper

Runtime checking C programs

Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2107โ€“2114.

By: R. Milewicz, R. Vanka, J. Tuckโ€‰, D. Quinlan & P. Pirkelbauer

Source: ORCID
Added: August 18, 2021

2015 conference paper

Source Mark: A Source-Level Approach for Identifying Architecture and Optimization Agnostic Regions for Performance Analysis

2015 IEEE International Symposium on Workload Characterization, 160โ€“171.

By: A. Agrawal, B. Wibowo & J. Tuckโ€‰

Event: IEEE

Source: ORCID
Added: August 18, 2021

2015 article

SourceMark: A Source-Level Approach for Identifying Architecture and Optimization Agnostic Regions for Performance Analysis

2015 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION (IISWC), pp. 160โ€“171.

By: A. Agrawal n, B. Wibowo n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: Web Of Science
Added: August 6, 2018

2014 conference paper

3D-enabled customizable embedded computer (3DECC)

2014 International 3D Systems Integration Conference (3DIC), 1โ€“3.

By: P. Franzon, E. Rotenberg, J. Tuckโ€‰, H. Zhou, W. Davis, H. Dai, J. Huh, S. Ku ...

Event: IEEE

Source: ORCID
Added: August 18, 2021

2014 journal article

Control-flow decoupling: An approach for timely, non-speculative branching

IEEE Transactions on Computers, 64(8), 2182โ€“2203.

By: R. Sheikh, J. Tuckโ€‰ & E. Rotenberg

Source: ORCID
Added: August 18, 2021

2013 conference paper

Applications and design styles for 3DIC

2013 IEEE International Electron Devices Meeting, 29โ€“24.

By: P. Franzon, E. Rotenberg, J. Tuckโ€‰, W. Davis, H. Zhou, J. Schabel, Z. Zhang, J. Park ...

Event: IEEE

Source: ORCID
Added: August 18, 2021

2013 journal article

Automatic Parallelization of Fine-Grained Metafunctions on a Chip Multiprocessor

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(4).

By: S. Lee n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Automatic parallelization; helper computing; chip multiprocessor
Sources: Web Of Science, ORCID
Added: August 6, 2018

2012 article

Control-Flow Decoupling

2012 IEEE/ACM 45TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-45), pp. 329โ€“340.

By: R. Sheikh n, J. Tuck nโ€‰ & E. Rotenberg n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: Web Of Science
Added: August 6, 2018

2012 conference paper

Control-flow decoupling

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 329โ€“340.

By: R. Sheikh, J. Tuckโ€‰ & E. Rotenberg

Event: IEEE

Source: ORCID
Added: August 18, 2021

2012 conference paper

Efficient and accurate data dependence profiling using software signatures

Proceedings of the Tenth International Symposium on Code Generation and Optimization, 186โ€“195.

By: R. Vanka & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2012 journal article

Efficiently Exploiting Memory Level Parallelism on Asymmetric Coupled Cores in the Dark Silicon Era

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(4).

By: G. Patsilaras n, N. Choudhary n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: Design; Performance; Memory level parallelism; multicore; asymmetric multicore processor; dark silicon
Sources: Web Of Science, ORCID
Added: August 6, 2018

2012 conference paper

HiRe: using hint & release to improve synchronization of speculative threads

HiRe: using hint & release to improve synchronization of speculative threads. Proceedings of the 26th ACM international conference on Supercomputing, 143โ€“152.

By: L. Han, X. Jiang, W. Liu, Y. Wu & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2011 journal article

Article 28 (21 pages)-Efficiently Exploiting Memory Level Parallelism on Asymmetric Coupled Cores in the Dark Silicon Era

ACM Transactions on Architecture and Code Optimization-TACO, 8(4).

By: G. Patsilaras, N. Choudhary & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2011 conference paper

AutoPipe: A Pipeline Parallelization Framework in GCC

GROW2011: International Workshop on GCC Research Opportunities.

By: S. Lee, J. Danis & J. Tuckโ€‰

Source: NC State University Libraries
Added: August 6, 2018

2011 conference paper

Automatic Parallelization of Fine-grained Meta-functions on a Chip Multiprocessor

International Symposium on Code Generation and Optimization, 130โ€“140.

By: S. Lee n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2011 conference paper

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

International symposium on high-performance computer, 99โ€“110.

By: S. Lee n, D. Tiwari n, S. Yanโ€‰ n & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: NC State University Libraries
Added: August 6, 2018

2011 conference paper

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

2011 IEEE 17th International Symposium on High Performance Computer Architecture, 99โ€“110.

By: S. Lee, D. Tiwari, Y. Solihin & J. Tuckโ€‰

Event: IEEE

Source: ORCID
Added: August 18, 2021

2011 journal article

SPECIAL ISSUE ON HIGH-PERFORMANCE AND EMBEDDED ARCHITECTURES AND COMPILERS

ACM Transactions On, 8(4).

By: P. Stenstrรถm, K. De Bosschere, J. Albericio, R. Gran, P. Ibรกรฑez, V. Viรฑals, J. LLaberฤฑฬa, A. Bayrak ...

Source: ORCID
Added: August 18, 2021

2010 conference paper

Design Trade-offs for Memory Level Parallelism on an Asymmetric Multicore System

Pespma 2010-Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture.

By: G. Patsilaras, N. Choudhary & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2010 conference paper

Design Tradeoffs for Memory-Level Parallelism on an Asymmetric Multicore System

Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures.

By: G. Patsilaras, N. Choudhary & J. Tuckโ€‰

Source: NC State University Libraries
Added: August 6, 2018

2010 conference paper

MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management

International Parallel and Distributed Processing Symposium.

By: D. Tiwariโ€‰ n, J. Tuck nโ€‰ & Y. Solihin n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: NC State University Libraries
Added: August 6, 2018

2010 conference paper

Mmt: Exploiting fine-grained parallelism in dynamic memory management

2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 1โ€“12.

By: D. Tiwari, S. Lee, J. Tuckโ€‰ & Y. Solihin

Event: IEEE

Source: ORCID
Added: August 18, 2021

2010 conference paper

Speculative parallelization of partial reduction variables

Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization, 141โ€“150.

By: L. Han n, W. Liuโ€‰* & J. Tuck nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2009 conference paper

Memory management thread for heap allocation intensive sequential applications

Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture, 35โ€“42.

By: D. Tiwariโ€‰ n, S. Leeโ€‰ n, J. Tuck nโ€‰ & Y. Solihin n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2009 journal article

SOFTSIG: SOFTWARE-EXPOSED HARDWARE SIGNATURES FOR CODE ANALYSIS AND OPTIMIZATION

IEEE MICRO, 29(1), 84โ€“95.

By: J. Tuck nโ€‰, W. Ahn*, J. Torrellasโ€‰* & L. Cezeโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: Web Of Science, ORCID
Added: August 6, 2018

2009 journal article

The Bulk Multicore Architecture for Improved Programmability

COMMUNICATIONS OF THE ACM, 52(12), 58โ€“65.

By: J. Torrellasโ€‰*, L. Cezeโ€‰*, J. Tuck nโ€‰, C. Cascaval*, P. Montesinos*, W. Ahn*, M. Prvulovicโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: Web Of Science, ORCID
Added: August 6, 2018

2008 report

A Data Dependence Profiler for the GNU Compiler Collection

In Technical Report- Not held in TRLN member libraries.

By: S. Gopal & J. Tuckโ€‰

Source: NC State University Libraries
Added: August 6, 2018

2008 conference paper

Parallelizing Mudflap Using Thread-Level Speculation on a CMP

Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures.

By: S. Lee & J. Tuckโ€‰

Source: NC State University Libraries
Added: August 6, 2018

2008 conference paper

Parallelizing Mudflap using Thread-Level Speculation on a Chip Multiprocessor

Proc. of the 2008 Workshop on Parallel Execution of Sequential Programs on Multicore Architectures, 72โ€“80.

By: S. Lee & J. Tuckโ€‰

Event: Citeseer

Source: ORCID
Added: August 18, 2021

2008 conference paper

SoftSig: Software Exposed Hardware Signatures for Code Analysis and Optimization

ACM International Symposium on Architectural Support for Programming Languages and Operating Systems, 145โ€“156.

By: J. Tuck nโ€‰, W. Ahn*, L. Cezeโ€‰* & J. Torrellasโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: NC State University Libraries
Added: August 6, 2018

2008 journal article

SoftSig: software-exposed hardware signatures for code analysis and optimization

ACM SIGOPS Operating Systems Review, 42(2), 145โ€“156.

By: J. Tuckโ€‰, W. Ahn, L. Ceze & J. Torrellas

Source: ORCID
Added: August 18, 2021

2008 article

System and method for cache coherency in a cache with different cache location lengths

(2008, November).

Source: ORCID
Added: August 18, 2021

2007 conference paper

BulkSC: Bulk enforcement of sequential consistency

Proceedings of the 34th annual international symposium on Computer architecture, 278โ€“289.

By: L. Cezeโ€‰*, J. Tuck*โ€‰, P. Montesinos* & J. Torrellasโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2007 conference paper

CAP: Criticality analysis for power-efficient speculative multithreading

2007 25th International Conference on Computer Design, 409โ€“416.

By: J. Tuck nโ€‰, W. Liuโ€‰* & J. Torrellasโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ

Event: IEEE

Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2007 report

Efficient support for speculative tasking

By: J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2006 conference paper

Are We Ready for High Memory-Level Parallelism?

Workshop on Memory Performance Issues.

By: L. Ceze, J. Tuckโ€‰ & J. Torrellas

Source: NC State University Libraries
Added: August 6, 2018

2006 conference paper

Are we ready for high memorylevel parallelism?

4th Workshop on Memory Performance Issues.

By: L. Ceze, J. Tuckโ€‰ & J. Torrellas

Source: ORCID
Added: August 18, 2021

2006 journal article

Boosting SMT trace processors performance with data cache misssensitive thread scheduling mechanism

Microprocessors and Microsystems, 30(5), 225โ€“233.

By: K. Wang, Z. Ji & M. Hu

Source: ORCID
Added: August 18, 2021

2006 conference paper

Bulk Disambiguation of Speculative Threads in Multiprocessors

IEEE/ACM Annual International Symposium on Computer Architecture, 227โ€“238.

By: L. Ceze, J. Tuckโ€‰, C. Cascaval & J. Torrellas

Source: NC State University Libraries
Added: August 6, 2018

2006 journal article

Bulk disambiguation of speculative threads in multiprocessors

ACM SIGARCH Computer Architecture News, 34(2), 227โ€“238.

By: L. Ceze, J. Tuckโ€‰, J. Torrellas & C. Cascaval

Source: ORCID
Added: August 18, 2021

2006 journal article

CAVA: Using checkpoint-assisted value prediction to hide L2 misses

ACM Transactions on Architecture and Code Optimization (TACO), 3(2), 182โ€“208.

By: L. Cezeโ€‰*, K. Straussโ€‰*, J. Tuck*โ€‰, J. Torrellasโ€‰* & J. Renau*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2006 journal article

Energy-Efficient Thread-Level Speculation on a CMP

IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, 80โ€“91.

By: J. Nenau, K. Strauss, L. Ceze, W. Liu, S. Sarangi, J. Tuckโ€‰, J. Torrellas

Source: NC State University Libraries
Added: August 6, 2018

2006 journal article

Energy-efficient thread-level speculation

IEEE Micro, 26(1), 80โ€“91.

By: J. Renau, K. Strauss, L. Ceze, W. Liu, S. Sarangi, J. Tuckโ€‰, J. Torrellas

Source: ORCID
Added: August 18, 2021

2006 conference paper

POSH: a TLS compiler that exploits program structure

Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, 158โ€“167.

By: W. Liuโ€‰*, J. Tuck*โ€‰, L. Cezeโ€‰*, W. Ahn*, K. Straussโ€‰*, J. Renau*, J. Torrellasโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2006 conference paper

Scalable cache miss handling for high memory-level parallelism

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 409โ€“422.

By: J. Tuck*โ€‰, L. Cezeโ€‰* & J. Torrellasโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ

Event: IEEE

Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2006 article

System and method for non-uniform cache in a multi-core processor

Hughes, C., Tuck, J., Lee, V., & Chen, Y.-kuang. (2006, June).

By: C. Hughes, J. Tuckโ€‰, V. Lee & Y. Chen

Source: ORCID
Added: August 18, 2021

2005 journal article

Languages and compilers for parallel computing

By: B. Tseng

Source: ORCID
Added: August 18, 2021

2005 conference paper

POSH: A profiler-enhanced TLS compiler that leverages program structure

IBM Watson P= AC2 Conference, 83โ€“92.

By: W. Liu, J. Tuckโ€‰, L. Ceze, K. Strauss, J. Renau & J. Torrellas

Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2005 article

SESC simulator, January 2005

By: J. Renau, B. Fraguela, J. Tuckโ€‰, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, P. Montesinos

Source: ORCID
Added: August 18, 2021

2005 conference paper

Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation

ACM International Conference on Supercomputing, 179โ€“188.

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: NC State University Libraries
Added: August 6, 2018

2005 conference paper

Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation

Proceedings of the 19th Annual International conference on Supercomputing, 179โ€“188.

By: J. Renau, J. Tuckโ€‰, W. Liu, L. Ceze, K. Strauss & J. Torrellas

Source: ORCID
Added: August 18, 2021

2005 conference paper

Thread-level speculation on a CMP can be energy efficient

Proceedings of the 19th annual international conference on Supercomputing, 219โ€“228.

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2004 journal article

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction

IEEE Computer Architecture Letters, 7โ€“10.

By: L. Ceze, K. Strauss, J. Tuckโ€‰ & J. Torrellas

Source: NC State University Libraries
Added: August 6, 2018

2004 journal article

CAVA: Hiding L2 misses with checkpoint-assisted value prediction

IEEE Computer Architecture Letters, 3(1), 7โ€“7.

By: L. Ceze, K. Strauss, J. Tuckโ€‰, J. Renau & J. Torrellas

Source: ORCID
Added: August 18, 2021

2003 thesis

A novel compiler framework for a chip-multiprocessor architecture with thread-level speculation

University of Illinois at Urbana-Champaign.

By: J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2002 journal article

Morphable multithreaded memory tiles (M3T) architecture

University of Illinois UIUC-CS Technical Report.

By: J. Renau, J. Tuckโ€‰, W. Liu & J. Torrellas

Source: ORCID
Added: August 18, 2021

2002 report

Sphinx Parallelization

By: J. Tuckโ€‰, L. Baugh, J. Renau & J. Torrellas

Source: ORCID
Added: August 18, 2021

2002 journal article

Sphinx parallelization

Dept. of Computer Science, University of Illinois, Tech. Rep. UIUCDCS.

By: L. Baugh, J. Renau, J. Tuckโ€‰ & J. Torrellas

Source: ORCID
Added: August 18, 2021

2001 journal article

Handling crosscutting constraints in domain-specific modeling

Communications of the ACM, 44(10), 87โ€“93.

By: J. Gray, T. Bapty, S. Neema & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

2001 journal article

Handling crosscutting constraints in domain-specific modeling - Uniting AOP with model-integrated computing.

COMMUNICATIONS OF THE ACM, 44(10), 87โ€“93.

By: J. Grayโ€‰*, T. Bapty*, S. Neema* & J. Tuck*โ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: Web Of Science, ORCID
Added: August 6, 2018

2001 journal article

Institute for Software Integrated Systems Vanderbilt University Nashville Tennessee 37235

ISIS, 1, 200.

By: J. Tuckโ€‰ & T. Bapty

Source: ORCID
Added: August 18, 2021

journal article

Abstract Parallel Operators: Revamping the Hardware/Software Interface for the Multicore Era

Patsilaras, G., Lee, S., & Tuck, J.

By: G. Patsilaras, S. Lee & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

journal article

Improving MemoiSE Using Function Splitting

Vanka, R., & Tuck, J.

By: R. Vanka & J. Tuckโ€‰

Source: ORCID
Added: August 18, 2021

report

Improving MemoiSE via Function Splitting

In Technical Report- Not held in TRLN member libraries (Vol. 2009).

Source: NC State University Libraries
Added: August 6, 2018

journal article

Industry Session Program Committee

Akin, B., Baghsorkhi, S., Bai, Y., Fletcher, C., Healy, M., Huang, M., โ€ฆ others.

By: B. Akin, S. Baghsorkhi, Y. Bai, C. Fletcher, M. Healy, M. Huang, O. Kayiran, S. Khan ...

Source: ORCID
Added: August 18, 2021

journal article

Tasking with out-of-order spawn in TLS chip multiprocessors

Tuck, J., & Torrellas, J.

By: J. Tuckโ€‰ & J. Torrellas

Source: ORCID
Added: August 18, 2021

journal article

Thread-Level Speculation on a CMP Can Be Energy Efficient

Strauss, J. R. K., Ceze, L., Liu, W., Sarangi, S., Tuck, J., & Torrellas, J.

By: J. Strauss, L. Ceze, W. Liu, S. Sarangi, J. Tuckโ€‰ & J. Torrellas

Source: ORCID
Added: August 18, 2021