James Murray Tuck

BBB: Simplifying Persistent Programming using Battery-Backed Buffers

2021 27TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA 2021).

DNA stability: a central design consideration for DNA data storage systems

[Review of ]. NATURE COMMUNICATIONS, 12(1).

Dolos: Improving the Performance of Persistent Applications in ADR-Supported Secure Memory

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture.

Promiscuous molecules for smarter file operations in DNA-based data storage

NATURE COMMUNICATIONS, 6.

Dynamic and scalable DNA-based information storage

NATURE COMMUNICATIONS, 11(1).

Methods of crash recovery for data stored in non-volatile main memory

Solihin, Y., Alshboul, M., & Tuck, J. (2020, March).

Persistent Data Retention Models

ArXiv Preprint ArXiv:2009.14705.

The Case for Domain-Specialized Branch Predictors for Graph-Processing

IEEE COMPUTER ARCHITECTURE LETTERS, 19(2), 101–104.

WET: write efficient loop tiling for non-volatile main memory

2020 57th ACM/IEEE Design Automation Conference (DAC), 1–6.

Driving the Scalability of DNA-Based Information Storage Systems

ACS SYNTHETIC BIOLOGY, 8(6), 1241–1248.

Dynamic DNA-based information storage

BioRxiv, 836429.

Dynamic modelling of the iron deficiency modulated transcriptome response in Arabidopsis thaliana roots

In Silico Plants, 1(1), diz005.

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2), 1–27.

Hardware supported permission checks on persistent objects for performance and programmability

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 466–478.

Inter-disciplinary research challenges in computer systems for the 2020s

National Science Foundation, USA, Tech. Rep.

Lazy persistency: A high-performing and write-efficient software persistency technique

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 439–451.

Characterizing the impact of soft errors across microarchitectural structures and implications for predictability

2017 IEEE International Symposium on Workload Characterization (IISWC), 250–260.

Efficient checkpointing of loop-based codes for non-volatile main memory

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), 318–329.

Hardware supported persistent object address translation

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 800–812.

Hiding the long latency of persist barriers using speculative execution

Proceedings of the 44th Annual International Symposium on Computer Architecture, 175–186.

Improving the effectiveness of searching for isomorphic chains in superword level parallelism

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 718–729.

Leveraging near data processing for high-performance checkpoint/restart

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 1–12.

Proteus: A flexible and fast software supported hardware logging approach for nvm

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 178–190.

ReDirect: Reconfigurable Directories for Multicore Architectures

ACM Transactions on Architecture and Code Optimization (TACO), 14(4), 1–23.

An accurate cross-layer approach for online architectural vulnerability estimation

ACM Transactions on Architecture and Code Optimization (TACO), 13(3), 1–27.

Languages and Compilers for Parallel Computing: 28th International Workshop, LCPC 2015, Raleigh, NC, USA, September 9-11, 2015, Revised Selected Papers

Springer.

Lightweight runtime checking of C programs with RTC

Computer Languages, Systems & Structures, 45, 191–203.

Clustering and Differential Alignment Algorithm: Identification of early stage regulators in the Arabidopsis thaliana iron deficiency response

PloS One, 10(8), e0136591.

Computational approaches to identify regulators of plant stress response using high-throughput gene expression data

Current Plant Biology, 3-4, 20–29.

Computing in 3D

2015 IEEE Custom Integrated Circuits Conference (CICC), 1–6.

Control-flow decoupling: An approach for timely, non-speculative branching

IEEE Transactions on Computers, 64(8), 2182–2203.

Runtime checking C programs

Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2107–2114.

Source Mark: A Source-Level Approach for Identifying Architecture and Optimization Agnostic Regions for Performance Analysis

2015 IEEE International Symposium on Workload Characterization, 160–171.

3D-enabled customizable embedded computer (3DECC)

2014 International 3D Systems Integration Conference (3DIC), 1–3.

Control-flow decoupling: An approach for timely, non-speculative branching

IEEE Transactions on Computers, 64(8), 2182–2203.

Applications and design styles for 3DIC

2013 IEEE International Electron Devices Meeting, 29–24.

Automatic parallelization of fine-grained metafunctions on a chip multiprocessor

ACM Transactions on Architecture and Code Optimization (TACO), 10(4), 1–26.

Control-flow decoupling

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 329–340.

Efficient and accurate data dependence profiling using software signatures

Proceedings of the Tenth International Symposium on Code Generation and Optimization, 186–195.

Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era

ACM Transactions on Architecture and Code Optimization (TACO), 8(4), 1–21.

HiRe: using hint & release to improve synchronization of speculative threads

HiRe: using hint & release to improve synchronization of speculative threads. Proceedings of the 26th ACM international conference on Supercomputing, 143–152.

Article 28 (21 pages)-Efficiently Exploiting Memory Level Parallelism on Asymmetric Coupled Cores in the Dark Silicon Era

ACM Transactions on Architecture and Code Optimization-TACO, 8(4).

AutoPipe: A Pipeline Parallelization Framework in GCC

GROW2011: International Workshop on GCC Research Opportunities.

Automatic Parallelization of Fine-grained Meta-functions on a Chip Multiprocessor

International Symposium on Code Generation and Optimization, 130–140.

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

International symposium on high-performance computer, 99–110.

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

2011 IEEE 17th International Symposium on High Performance Computer Architecture, 99–110.

SPECIAL ISSUE ON HIGH-PERFORMANCE AND EMBEDDED ARCHITECTURES AND COMPILERS

ACM Transactions On, 8(4).

Design Trade-offs for Memory Level Parallelism on an Asymmetric Multicore System

Pespma 2010-Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture.

Design Tradeoffs for Memory-Level Parallelism on an Asymmetric Multicore System

Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures.

MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management

International Parallel and Distributed Processing Symposium.

Mmt: Exploiting fine-grained parallelism in dynamic memory management

2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 1–12.

Speculative parallelization of partial reduction variables

Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization, 141–150.

Memory management thread for heap allocation intensive sequential applications

Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture, 35–42.

Softsig: Software-exposed hardware signatures for code analysis and optimization

IEEE Micro, 29(1), 84–95.

The Bulk Multicore for Improved Programmability

Communications of the ACM.

The bulk multicore architecture for improved programmability

Communications of the ACM, 52(12), 58–65.

A Data Dependence Profiler for the GNU Compiler Collection

In Technical Report- Not held in TRLN member libraries.

Parallelizing Mudflap Using Thread-Level Speculation on a CMP

Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures.

Parallelizing Mudflap using Thread-Level Speculation on a Chip Multiprocessor

Proc. of the 2008 Workshop on Parallel Execution of Sequential Programs on Multicore Architectures, 72–80.

SoftSig: Software Exposed Hardware Signatures for Code Analysis and Optimization

ACM International Symposium on Architectural Support for Programming Languages and Operating Systems, 145–156.

SoftSig: software-exposed hardware signatures for code analysis and optimization

ACM SIGOPS Operating Systems Review, 42(2), 145–156.

System and method for cache coherency in a cache with different cache location lengths

(2008, November).

BulkSC: Bulk enforcement of sequential consistency

Proceedings of the 34th annual international symposium on Computer architecture, 278–289.

CAP: Criticality analysis for power-efficient speculative multithreading

2007 25th International Conference on Computer Design, 409–416.

Efficient support for speculative tasking

Are We Ready for High Memory-Level Parallelism?

Workshop on Memory Performance Issues.

Are we ready for high memorylevel parallelism?

4th Workshop on Memory Performance Issues.

Boosting SMT trace processors performance with data cache misssensitive thread scheduling mechanism

Microprocessors and Microsystems, 30(5), 225–233.

Bulk Disambiguation of Speculative Threads in Multiprocessors

IEEE/ACM Annual International Symposium on Computer Architecture, 227–238.

Bulk disambiguation of speculative threads in multiprocessors

ACM SIGARCH Computer Architecture News, 34(2), 227–238.

CAVA: Using checkpoint-assisted value prediction to hide L2 misses

ACM Transactions on Architecture and Code Optimization (TACO), 3(2), 182–208.

Energy-Efficient Thread-Level Speculation on a CMP

IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, 80–91.

Energy-efficient thread-level speculation

IEEE Micro, 26(1), 80–91.

POSH: a TLS compiler that exploits program structure

Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, 158–167.

Scalable cache miss handling for high memory-level parallelism

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 409–422.

System and method for non-uniform cache in a multi-core processor

Hughes, C., Tuck, J., Lee, V., & Chen, Y.-kuang. (2006, June).

Languages and compilers for parallel computing

POSH: A profiler-enhanced TLS compiler that leverages program structure

IBM Watson P= AC2 Conference, 83–92.

SESC simulator, January 2005

Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation

ACM International Conference on Supercomputing, 179–188.

Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation

Proceedings of the 19th Annual International conference on Supercomputing, 179–188.

Thread-level speculation on a CMP can be energy efficient

Proceedings of the 19th annual international conference on Supercomputing, 219–228.

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction

IEEE Computer Architecture Letters, 7–10.

CAVA: Hiding L2 misses with checkpoint-assisted value prediction

IEEE Computer Architecture Letters, 3(1), 7–7.

A novel compiler framework for a chip-multiprocessor architecture with thread-level speculation

University of Illinois at Urbana-Champaign.

Morphable multithreaded memory tiles (M3T) architecture

University of Illinois UIUC-CS Technical Report.

Sphinx Parallelization

Sphinx parallelization

Dept. of Computer Science, University of Illinois, Tech. Rep. UIUCDCS.

Handling Crosscutting Constraints in Domain-Speci?c Modeling

Communications of the ACM, 44(10), 87–93.

Handling crosscutting constraints in domain-specific modeling

Communications of the ACM, 44(10), 87–93.

Institute for Software Integrated Systems Vanderbilt University Nashville Tennessee 37235

ISIS, 1, 200.

Abstract Parallel Operators: Revamping the Hardware/Software Interface for the Multicore Era

Patsilaras, G., Lee, S., & Tuck, J.

Improving MemoiSE Using Function Splitting

Vanka, R., & Tuck, J.

Improving MemoiSE via Function Splitting

In Technical Report- Not held in TRLN member libraries (Vol. 2009).

Industry Session Program Committee

Akin, B., Baghsorkhi, S., Bai, Y., Fletcher, C., Healy, M., Huang, M., … others.

Tasking with out-of-order spawn in TLS chip multiprocessors

Tuck, J., & Torrellas, J.

Thread-Level Speculation on a CMP Can Be Energy Efficient

Strauss, J. R. K., Ceze, L., Liu, W., Sarangi, S., Tuck, J., & Torrellas, J.