Luis Francisco

College of Engineering

Works (5)

Updated: July 5th, 2023 15:07

2022 journal article

A Deep Transfer Learning Design Rule Checker With Synthetic Training

IEEE Design & Test, 40(1), 77–84.

By: L. Francisco n, W. Davis n & P. Franzon n 

author keywords: Layout; Design methodology; Convolutional neural networks; Transfer learning; Generators; Deep learning; Manuals; Training data; Design Rule Checking; Machine Learning; IC Verification; Physical Verification; Convolutional Neural Network; Deep Learning; Synthetic Data Training; Transfer Learning
topics (OpenAlex): Machine Learning and Data Classification; Hydraulic and Pneumatic Systems; Advanced Multi-Objective Optimization Algorithms; Model Reduction and Neural Networks
Sources: Web Of Science, ORCID, NC State University Libraries, Crossref
Added: January 24, 2023

2021 article

Fast and Accurate PPA Modeling with Transfer Learning

Francisco, L., Franzon, P., & Davis, W. R. (2021, August 30). 2021 ACM/IEEE 3RD WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD).

By: L. Francisco n, P. Franzon n  & W. Davis n 

author keywords: PPA; Machine Learning; Power; Performance; Area; Gradient Boost; Neural Network; Transfer Learning
topics (OpenAlex): VLSI and FPGA Design Techniques; VLSI and Analog Circuit Testing; Low-power high-performance VLSI design
TL;DR: This work presents a machine learning approach using gradient boost models and neural networks to fast and accurately predict the power, performance, and area of a System-on-Chip (SoC) by reducing the number of samples used to create the models. (via Semantic Scholar)
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Sources: Web Of Science, NC State University Libraries
Added: November 15, 2021

2021 conference paper

Fast and Accurate PPA Modeling with Transfer Learning

By: W. Davis n , P. Franzon n , L. Francisco n, B. Huggins n & R. Jain *

author keywords: PPA; Machine Learning; Power; Performance; Area; Gradient Boost; Neural Network; Transfer Learning; Surrogate Modeling
topics (OpenAlex): VLSI and FPGA Design Techniques; Low-power high-performance VLSI design; Advanced Multi-Objective Optimization Algorithms
TL;DR: The approach reached the same PPA solution as human designers in the same or fewer runs for a CORTEX-M0 system design, showing potential for automating the recipe optimization without needing more runs than a human designer would need. (via Semantic Scholar)
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9. Industry, Innovation and Infrastructure (OpenAlex)
Sources: Web Of Science, NC State University Libraries, Crossref
Added: February 21, 2022

2020 article

Design Rule Checking with a CNN Based Feature Extractor

Francisco, L., Lagare, T., Jain, A., Chaudhary, S., Kulkarni, M., Sardana, D., … Franzon, P. (2020, November 16). PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20).

By: L. Francisco n, T. Lagare n, A. Jain  n, S. Chaudhary n, M. Kulkarni  n, D. Sardana n, W. Davis n , P. Franzon n 

author keywords: Design Rule Checking; Machine Learning; IC Verification; Design for Manufacturing; Convolutional Neural Network; Deep Learning
topics (OpenAlex): VLSI and Analog Circuit Testing; Advancements in Photolithography Techniques; VLSI and FPGA Design Techniques
TL;DR: The proof of feasibility for a fast interactive DRC engine that could be used during layout is established and the proposed model consists of a convolutional neural network trained to detect DRC violations. (via Semantic Scholar)
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Sources: Web Of Science, NC State University Libraries
Added: August 16, 2021

2019 article

Multilayer CMP hotspot modeling through deep learning

Francisco, L., Mao, R., Katakamsetty, U., Verma, P., & Pack, R. C. (2019, March 20).

By: L. Francisco n, R. Mao *, U. Katakamsetty*, P. Verma * & R. Pack *

author keywords: CMP; Machine Learning; DFM; Advanced Lithography; Depth of Focus; CMP hotspots; Chip Topography
topics (OpenAlex): Advanced Surface Polishing Techniques; Integrated Circuits and Semiconductor Failure Analysis; Advancements in Photolithography Techniques
TL;DR: A Deep Learning (DL) multilayer convolutional neural network (CNN) algorithm is used to model CMP hotspots for full-chip multilayers layouts enabling modeling and prediction of hotspots resulting from complex inter-layer interactions or effects which may escape traditional methods. (via Semantic Scholar)
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Source: Web Of Science
Added: November 11, 2019

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