@article{francisco_davis_franzon_2023, title={A Deep Transfer Learning Design Rule Checker With Synthetic Training}, volume={40}, ISSN={["2168-2364"]}, url={https://doi.org/10.1109/MDAT.2022.3162786}, DOI={10.1109/MDAT.2022.3162786}, abstractNote={Deep transfer learning is applied to the task of design rule checking (DRC). A parameterized synthetic data set generator is used to train the model. —Ulf Schlichtmann, Technical University of Munich}, number={1}, journal={IEEE DESIGN & TEST}, author={Francisco, Luis and Davis, W. Rhett and Franzon, Paul}, year={2023}, month={Feb}, pages={77–84} }
 @article{francisco_franzon_davis_2021, title={Fast and Accurate PPA Modeling with Transfer Learning}, DOI={10.1109/MLCAD52597.2021.9531109}, abstractNote={The power, performance, and area (PPA) of a System-on-Chip (SoC) is known only after a months-long process. This process includes iterations over the architectural design, register transfer level implementation, RTL synthesis, and place and route. Knowing the PPA estimates for a system early in the design stages can help resolve tradeoffs that will affect the final design. This work presents a machine learning approach using gradient boost models and neural networks to fast and accurately predict the PPA. This work focuses on reducing the number of samples used to create the models. The models use transfer learning to predict the PPA for new design configurations and corner conditions based on previous models. The models predict the PPA as a function of parameters accessible during the RTL synthesis. The proposed models achieved PPA predictions up to 99% accurate and using as few as 10 data samples can achieve accuracies better than 96%.}, journal={2021 ACM/IEEE 3RD WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD)}, author={Francisco, Luis and Franzon, Paul and Davis, W. Rhett}, year={2021} }
 @inproceedings{davis_franzon_francisco_huggins_jain_2021, title={Fast and Accurate PPA Modeling with Transfer Learning}, ISSN={["1933-7760"]}, DOI={10.1109/ICCAD51958.2021.9643533}, abstractNote={The power, performance and area (PPA) of digital blocks can vary 10:1 based on their synthesis, place, and route tool recipes. With rapid increase in number of PVT corners and complexity of logic functions approaching 10M gates, industry has an acute need to minimize the human resources, compute servers, and EDA licenses needed to achieve a Pareto optimal recipe. We first present models for fast accurate PPA prediction that can reduce the manual optimization iterations with EDA tools. Secondly we investigate techniques to automate the PPA optimization using evolutionary algorithms. For PPA prediction, a baseline model is trained on a known design using Latin hypercube sample runs of the EDA tool, and transfer learning is then used to train the model for an unseen design. For a known design the baseline needed 150 training runs to achieve a 95% accuracy. With transfer learning the same accuracy was achieved on a different (unseen) design in only 15 runs indicating the viability of transfer learning to generalize PPA models. The PPA optimization technique, based on evolutionary algorithms, effectively combines the PPA modeling and optimization. Our approach reached the same PPA solution as human designers in the same or fewer runs for a CORTEX-M0 system design. This shows potential for automating the recipe optimization without needing more runs than a human designer would need.}, booktitle={2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)}, author={Davis, W.R. and Franzon, P. and Francisco, L. and Huggins, B. and Jain, R.}, year={2021} }
 @article{francisco_lagare_jain_chaudhary_kulkarni_sardana_davis_franzon_2020, title={Design Rule Checking with a CNN Based Feature Extractor}, DOI={10.1145/3380446.3430625}, abstractNote={Design rule checking (DRC) is getting increasingly complex in advanced nodes technologies. It would be highly desirable to have a fast interactive DRC engine that could be used during layout. In this work, we establish the proof of feasibility for such an engine. The proposed model consists of a convolutional neural network (CNN) trained to detect DRC violations. The model was trained with artificial data that was derived from a set of 50 SRAM designs. The focus in this demonstration was metal 1 rules. Using this solution, we can detect multiple DRC violations 32x faster than Boolean checkers with an accuracy of up to 92%. The proposed solution can be easily expanded to a complete rule set.}, journal={PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20)}, author={Francisco, Luis and Lagare, Tanmay and Jain, Arpit and Chaudhary, Somal and Kulkarni, Madhura and Sardana, Divya and Davis, W. Rhett and Franzon, Paul}, year={2020}, pages={9–14} }
 @article{francisco_mao_katakamsetty_verma_pack_2019, title={Multilayer CMP Hotspot Modeling Through Deep Learning}, volume={10962}, ISBN={["978-1-5106-2571-6"]}, ISSN={["1996-756X"]}, DOI={10.1117/12.2514467}, abstractNote={Chemical mechanical polishing (CMP) is a critical process in Integrated Circuit (IC) manufacturing used to ensure planarity of the layers which comprise the IC. The IC design and CMP process must be optimally integrated otherwise dishing and erosion may occur on any of the various layers resulting in significant degradation impacting lithographic pattern fidelity and performance variability. Consequently, it is desirable to accurately predict if and where these hotspots (HS) will appear early in the design to ensure high manufacturing yield and predicted performance. In this work, we use a Deep Learning (DL) multilayer convolutional neural network (CNN) algorithm to model CMP hotspots for full-chip multilayer layouts. The DL model consists of convolutional layers for automatic feature extraction and fully-connected CNN layers for HS classification and detection. Our implementation can learn/capture effects that go beyond traditional methods in that these effects can be discovered from previous technologies with transfer learning and the model can be trained with either simulation or topography measurement data. Further, the model is trained from multiple layers and CMP results thereby enabling modeling and prediction of hotspots resulting from complex inter-layer interactions or effects which may escape traditional methods. With the proposed DL model, we achieved a hotspot prediction accuracy of up to 98% with up to 10 metal layers. After training the model, the inference time for a full chip can be up to 10x faster than existing CMP tools. This flow enables CMP/Fill-aware design validation that can help to create optimal high-yielding customer designs.}, journal={DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIII}, author={Francisco, Luis and Mao, Rui and Katakamsetty, Ushasree and Verma, Piyush and Pack, Robert}, year={2019} }