@article{moorthy_aberg_olimmah_yang_rahman_lemmon_yu_husain_2020, title={Estimation, Minimization, and Validation of Commutation Loop Inductance for a 135-kW SiC EV Traction Inverter}, volume={8}, ISSN={["2168-6785"]}, DOI={10.1109/JESTPE.2019.2952884}, abstractNote={With growing interests in low-inductance silicon carbide (SiC)-based power module packaging, it is vital to focus on system-level design aspects to facilitate easy integration of the modules and reap system-level benefits. To effectively utilize the low-inductance modules, busbar and interconnects should also be designed with low stray inductances. A holistic investigation of the flux path and flux cancellations in the module-busbar assembly, which can be treated as differentially coupled series inductors, is thus mandatory for a system-level design. This article presents a busbar design, which can be adopted to effectively integrate the CREE’s low-inductance 1.2-/1.7-kV SiC power modules. This article also proposes a novel measurement technique to measure the inductance of the module-busbar assembly as a whole rather than deducing it from individual components. The inductance of the overall commutation loop of the inverter that encompasses the SiC power module, interconnects, and printed circuit board (PCB) busbar has been estimated using finite-element analysis (FEA). Insights gained from FEA provided the guidelines to decide the placement of the decoupling capacitors in the busbar to minimize the overall commutation loop inductance from 12.8 to 7.4 nH, which resulted in a significant reduction in the device voltage overshoot. The simulation results have been validated through measurements using an impedance analyzer (ZA) with less than 5% difference between the extracted loop inductance from FEA and measurements. The busbar design study and the measurement technique discussed in this article can be easily extended to other power module packages. Finally, the 135-kW inverter has been compared to a similar high-power inverter utilizing a laminated busbar to highlight the performance of the former.}, number={1}, journal={IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS}, author={Moorthy, Radha Sree Krishna and Aberg, Bryce and Olimmah, Marshal and Yang, Li and Rahman, Dhrubo and Lemmon, Andrew N. and Yu, Wensong and Husain, Iqbal}, year={2020}, month={Mar}, pages={286–297} }
 @inproceedings{yang_gao_yu_husain_2017, title={A geometrical linearization approach for salient-pole PMSM optimal voltage/current constrained control over whole speed range}, DOI={10.1109/ecce.2017.8095803}, abstractNote={Permanent Magnet Synchronous Machine (PMSM) torque control over a wide speed range is essentially an optimization problem that treats torque error minimization as the objective function with inverter voltage and current as constraints. It is usually time consuming and difficult to solve such optimization problem for closed-form solutions since torque, voltage and current equations are all non-linear in the problem. In this paper, a model linearization based approach is proposed to manage the calculation complexity for such non-linear optimization. By dividing the problem into two sub-optimizations and solving them sequentially, the calculation is simplified. By identifying different operating regions of the PMSM, the closed-form solutions can be obtained geometrically with model linearization, which further simplifies the optimization process. The proposed algorithm is implemented for PMSM current loop controller design; simulation results show a good performance of the controller.}, booktitle={2017 ieee energy conversion congress and exposition (ecce)}, author={Yang, L. and Gao, R. and Yu, Wensong and Husain, I.}, year={2017}, pages={350–356} }
 @inproceedings{gao_yang_yu_husain_2017, title={Gate driver design for a high power density EV/HEV traction driveu using silicon carbide MOSFET six-pack power modules}, DOI={10.1109/ecce.2017.8096484}, abstractNote={Targeting the development of a silicon carbide (SiC) inverter for electric vehicle/hybrid electric vehicle (EV/HEV) applications, the design considerations of the gate driver for the adopted SiC metal-oxide-semiconductor field-transistor (MOSFET) power modules are presented. Given the system power density requirement, the gate driver design challenges for the commercial off-the-shelf (COTS) SiC modules are identified, analyzed, and tackled with proposed solutions. To accomplish such design with the constraint of limited layout space, a single chip MAX 13256 (3 mm×3 mm) enabled high frequency link based isolated bias supply structure is proposed for each six-pack module. Moreover, the gate driver design guidelines for module phase-leg parallel operation are introduced with a comparison study confirming the printed circuit board (PCB) layout effectiveness for electromagnetic interference (EMI) mitigation. Experimental validation is conducted on the traction inverter prototype.}, booktitle={2017 ieee energy conversion congress and exposition (ecce)}, author={Gao, R. and Yang, L. and Yu, Wensong and Husain, I.}, year={2017}, pages={2546–2551} }
 @inproceedings{gao_yang_yu_husain_2016, title={Single chip enabled high frequency link based isolated bias supply for silicon carbide MOSFET six-pack power module gate drives}, DOI={10.1109/ecce.2016.7855435}, abstractNote={Regarded as one of the most successful wide bandgap (WBG) devices, Silicon Carbide (SiC) metal-oxide-semiconductor field-transistors (MOSFETs) are being considered in an increasing number of power electronics applications. One of those applications is the hybrid and electric vehicle (HEV/EV) traction inverters where high-efficiency and high-power density is essential. From the system-level perspective, the gate driver circuit design for such device is challenging considering the device's fast switching speed and compact system structure. This paper presents a low profile (6 mm) isolated bias supply design using commercially available components for the SiC MOSFET modules targeting an HEV/EV traction inverter application. A single chip MAX 13256 (3 mm∗3 mm) is adopted to form the high-frequency link for entire power module gate drive supply. Distributed transformer strategy is highlighted to provide multiple isolated output and compact structure with minimized parasitic capacitance between all the isolation barriers. The featured low profile optimization reduces the parasitic parameters that might deteriorate the system performance for the fast switching WBG devices. Moreover, the open-loop high-frequency link architecture allows easy configuration for customized output voltage level, polarity and higher reliability. A prototype gate driver has been built for 1.2 kV, 50 A SiC six-pack MOSFET power module, and experimental results are presented.}, booktitle={2016 ieee energy conversion congress and exposition (ecce)}, author={Gao, R. and Yang, L. and Yu, Wensong and Husain, I.}, year={2016} }