Works (6)

Updated: July 5th, 2023 15:30

2021 article

BBB: Simplifying Persistent Programming using Battery-Backed Buffers

2021 27TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA 2021), pp. 111–124.

TL;DR: BBB simplifies persistent programming as the programmer does not need to insert persist barriers or flushes, and achieves nearly identical results to eADR in terms of performance and number of NVMM writes, while requiring two orders of magnitude smaller energy and time to drain. (via Semantic Scholar)
UN Sustainable Development Goal Categories
Sources: Web Of Science, NC State University Libraries
Added: July 26, 2021

2019 journal article

Compiler-support for Critical Data Persistence in NVM

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(4).

author keywords: Compiler-support; NVM; data persistence; valid recovery
TL;DR: This article presents a compiler-support that automatically inserts complex instructions into kernels to achieve NVM data-persistence based on a simple programmer directive and shows that the proposed compiler- support outperforms the most recent checkpointing techniques while its performance overheads are insignificant. (via Semantic Scholar)
Source: Web Of Science
Added: January 13, 2020

2019 journal article

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2).

By: M. Alshboul n, H. Elnawawy n, R. Elkhouly*, K. Kimura*, J. Tuck n & Y. Solihin*

author keywords: Memory systems; emerging memory technologies; computer architecture
TL;DR: A novel recompute-based failure safety approach that removes the need to keep checkpoints or logs, thus reducing execution time overheads and improving NVMM write endurance at the expense of more complex recovery. (via Semantic Scholar)
Source: Web Of Science
Added: August 5, 2019

2019 conference paper

Exploring Memory Persistency Models for GPUs

28th International Conference on Parallel Architectures and Compilation Techniques (PACT), 310–322.

By: Z. Lin n, M. Alshboul n, Y. Solihin* & H. Zhou n

Event: International Conference on Parallel Architectures and Compilation Techniques at Seattle, WA on September 21-25, 2019

TL;DR: This paper adapt, re-architect, and optimize CPU persistency models for GPU, and design a pragma-based compiler scheme for expressing persistency model for GPUs, and identifies that the thread hierarchy in GPUs offers intuitive scopes to form epochs and durable transactions. (via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries
Added: August 10, 2020

2018 article

Characterizing Realistic Signature-based Intrusion Detection Benchmarks

PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY: IOT AND SMART CITY (ICIT 2018), pp. 97–103.

By: M. Aldwairi*, M. Alshboul n & A. Seyam*

author keywords: Intrusion detection; Pattern matching; Benchmarks; Attack signatures; Traffic traces
TL;DR: A pattern-matching engine that enables researchers to plug-and-play their new pattern matching algorithms and compare to existing algorithms using the predefined metrics, and a generic parser capable of parsing different intrusion detection systems rule formats and extract attack signatures are provided. (via Semantic Scholar)
Source: Web Of Science
Added: July 1, 2019

2018 article

Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique

2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 439–451.

By: M. Alshboul n, J. Tuck n & Y. Solihin n

author keywords: Emerging Memory Technology; Memory Systems; Multi-core and Parallel Architectures
TL;DR: This work proposes Lazy Persistency (LP), a software persistency technique that allows caches to slowly send dirty blocks to the NVMM through natural evictions, and reduces the execution time and write amplification overheads from 9% and 21% to only 1% and 3%, respectively. (via Semantic Scholar)
Source: Web Of Science
Added: March 4, 2019

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