@inproceedings{evaluation and comparison of 3.0 nm gate-stack dielectrics for tenth-micron technology nmosfets_1998, booktitle={Rapid thermal and integrated processing VII: Symposium held April 13-15, 1998, San Francisco, California, U.S.A.  (Materials Research Society symposium proceedings ; v.525)}, publisher={Warrendale, Pennsylvania: Materials Research Society}, year={1998}, pages={157–162} }
 @article{srivastava_heinisch_vogel_parker_osburn_masnari_wortman_hauser_1998, title={Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs}, volume={525}, ISBN={["1-55899-431-9"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-525-163}, abstractNote={ABSTRACT}, journal={RAPID THERMAL AND INTEGRATED PROCESSING VII}, author={Srivastava, A and Heinisch, HH and Vogel, E and Parker, C and Osburn, CM and Masnari, NA and Wortman, JJ and Hauser, JR}, year={1998}, pages={163–170} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1998, title={Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors}, volume={145}, ISSN={["1945-7111"]}, DOI={10.1149/1.1838607}, abstractNote={Device drive current, parasitic resistance, and junction leakage current have been studied using silicided and non-silicided deep submicron elevated source/drain (ESD) n-channel metal oxide semiconductor field effect transistors (NMOSFETs). This study illustrated the effects of doping profile in the elevated S/D region, junction depth in the substrate, and doping level in the source/drain extension. Compared to devices having nonelevated junctions with the same substrate doping profile, MOSFETs with a profile-doped elevated S/D, used to contact an ultrashallow junction formed before selective epitaxial growth, had higher drive currents and demonstrated the ability of the elevated junction to reduce the extrinsic resistance. Measurements of drive currents in ESD devices showed that (i) the lightly doped region at the bottom of a profile-doped elevated layer introduces additional extrinsic resistance, and (ii) the locally deeper junction beneath the epi facets extends laterally toward the channel and shortens the drain extension length, thereby reducing the intrinsic resistance. Silicided devices had higher drive current and reduced parasitic resistance when the silicide/silicon interfacial dopant concentrations remained high (>1 x 10 20 /cm 3 ) after silicidation. The lowest total parasitic resistance was achieved when the elevated S/D was used to give a small contact resistance to a shallow junction and a moderately doped drain extension was used to lower the resistance of the source/drain extension tab.}, number={6}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Sun, J and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA and Westhoff, R}, year={1998}, month={Jun}, pages={2131–2137} }
 @inproceedings{srivastava_sun_bellur_bartholomew_o'neil_celik_osburn_masnari_ozturk_westhoff_et al._1997, title={A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy}, booktitle={ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3)}, publisher={Pennington, NJ: Electrochemical Society}, author={Srivastava, A. and Sun, J. and Bellur, K. and Bartholomew, R. F. and O'Neil, P. and Celik, S. M. and Osburn, C. M. and Masnari, N. A. and Ozturk, M. C. and Westhoff, R. and et al.}, year={1997}, pages={571–585} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1997, title={A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors}, volume={144}, ISSN={["1945-7111"]}, DOI={10.1149/1.1838066}, abstractNote={Ultrashallow elevated n'/p junctions (∼75 nm) incorporating selectively deposited epitaxial silicon layers were fabricated. The undoped epi layers (∼100 nm) were deposited on exposed diffusion areas in an Advanced Semiconductor Material Epsilon I system specifically designed for low thermal budget single-wafer processing. Shallow junctions (∼75 nm) were formed by ion implantation (As, 4 x 10 15 /cm 2 , 80 keV) into undoped epi layers and out-diffusion into the underlying substrate. Alternatively, an ion implanted (As, 4 x 10 15 /cm 2 , 60 keV) elevated layer was utilized to contact a shallow junction, which was formed (As, 1.5 x 10 15 /cm 2 , 15 keV) before the epi deposition. All junctions were annealed at 950°C for 10 s. Nonsilicided elevated junctions and conventional nonelevated (As, 1.5 x 10 15 /cm 2 , 15 keV) ones displayed very similar junction characteristics. Silicided nonelevated ultrashallow junctions, however, showed large reverse leakage current due to the substrate consumption. Both silicided elevated (post-epi and pre-epi) junctions exhibited excellent forward characteristics and low reverse leakage current. The difference in the reverse leakage characteristics of these two elevated junctions was attributed to the epi faceting formed at the sidewall edge of localized oxidation of silicon isolation. Deep submicron n = channel metal oxide semiconductor field effect transistors incorporating these junctions were also fabricated and electrically tested. Both elevated source/drain (S/D) devices show superior current driving capability compared to nonelevated ones as a result of much reduced parasitic resistance from contact source/drain junctions.}, number={10}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Sun, J and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA and Westhoff, R}, year={1997}, month={Oct}, pages={3659–3664} }
 @inproceedings{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1997, title={Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology}, booktitle={ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3)}, publisher={Pennington, NJ: Electrochemical Society}, author={Sun, J. and Bartholomew, R. F. and Bellur, K. and Srivastava, A. and Osburn, C. M. and Masnari, N. A. and Westhoff, R.}, year={1997}, pages={587–597} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_1997, title={The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's}, volume={44}, ISSN={["0018-9383"]}, DOI={10.1109/16.622606}, abstractNote={Deep submicron NMOSFETs with elevated source/drain (ESD) were fabricated using self-aligned selective epitaxial deposition and engineered ion implanted profiles in the elevated layers, Deeper source/drain (S/D) junctions give rise to improved drive current over shallower profiles when the same spacer thickness and LDD doping level are used, Shallower junctions, especially with the heavily-doped S/D residing in the elevated layer, give better immunity to drain-induced-barrier lowering (DLBL) and bulk punchthrough. Tradeoffs between short-channel behavior and drive current with regard to S/D junction depth and spacer thickness were further studied using process/device simulations to cover a broader range of structure parameters. Despite the existence of epi facets along the sidewall spacers, the elevated S/D could be used as a sacrificial layer for silicidation, without degradation of the low-leakage junctions. The effects of the elevated S/D doping profile on substrate current and hot-electron-induced degradation were measured and analyzed. The simulated results were used, for the first time, to define the range of spacer thickness and LDD doses that are required in order for the lightly-doped region in the elevated S/D to effectively suppress the lateral electric field.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sun, JJ and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA}, year={1997}, month={Sep}, pages={1491–1498} }
 @article{sun_bartholomew_bellur_oneil_srivastava_violette_ozturk_osburn_masnari_1996, title={Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition}, volume={429}, ISBN={["1-55899-332-0"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-429-343}, abstractNote={Abstract}, journal={RAPID THERMAL AND INTEGRATED PROCESSING V}, author={Sun, J and Bartholomew, RF and Bellur, K and ONeil, PA and Srivastava, A and Violette, KE and Ozturk, MC and Osburn, CM and Masnari, NA}, year={1996}, pages={343–347} }
 @article{tian_kim_hauser_masnari_littlejohn_1995, title={Effects of profile doped elevated source/drain structures on deep-submicron MOSFETs}, volume={38}, ISSN={0038-1101}, url={http://dx.doi.org/10.1016/0038-1101(94)00160-H}, DOI={10.1016/0038-1101(94)00160-H}, abstractNote={Computer simulations have been carried out to systematically evaluate and compare device characteristics for various profile doped elevated source/drain (ESD) 0.25 μm channel-length MOSFET structures. In particular, characteristics for MOSFETs with a gradual profile doped ESD and for MOSFETs with an abrupt profile N+-N− doped ESD are examined in detail. Design considerations for key parameters related to the ESD formation (such as sidewall oxide width, elevation height and source/drain doping profile) and their influences on device characteristics are discussed. The results show the importance of ESD design parameters and structural optimization. They also indicate that the proposed gradual profile doped ESD MOSFETs can be as effective as the abrupt profile N+-N− doped ESD MOSFETs in achieving overall performance enhancement and reliability for deep-submicron device applications.}, number={3}, journal={Solid-State Electronics}, publisher={Elsevier BV}, author={Tian, H. and Kim, K.W. and Hauser, J.R. and Masnari, N.A. and Littlejohn, M.A.}, year={1995}, month={Mar}, pages={573–579} }
 @article{tian_hulfachor_ellis-monaghan_kim_littlejohn_hauser_masnari_1994, title={An evaluation of super-steep-retrograde channel doping for deep-submicron MOSFET applications}, volume={41}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.324605}, DOI={10.1109/16.324605}, abstractNote={Performance and reliability of deep-submicron MOSFET's employing super-steep-retrograde (SSR) channel doping configurations are examined using self-consistent Monte Carlo and drift-diffusion simulations. It is found that SSR channel doped MOSFET's provide increased current drive and reduced threshold voltage shift when compared with conventional MOSFET structures. However, they also display a relatively higher substrate current and interface state generation rate. The physical mechanisms of performance enhancement/degradation and design tradeoffs for SSR channel doped MOSFET's are discussed. >}, number={10}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Tian, H. and Hulfachor, R.B. and Ellis-Monaghan, J.J. and Kim, K.W. and Littlejohn, M.A. and Hauser, J.R. and Masnari, N.A.}, year={1994}, pages={1880–1882} }
 @article{masnari_1994, title={SINGLE-WAFER PROCESS INTEGRATION FOR SUBMICRON STRUCTURES}, volume={12}, ISSN={["1071-1023"]}, DOI={10.1116/1.587186}, abstractNote={As semiconductor technology moves toward reduced feature size, increased device density, and larger diameter wafers, there is increasing need for reliable, economical, in situ, single-wafer processing under low-thermal budget conditions. Two promising techniques to do this are rapid thermal processing and remote plasma-enhanced chemical vapor deposition. The integration of such processing techniques together with proper surface preparation has significant potential for meeting the fabrication needs at the deep submicron level. The extension of such in situ processing to include the clustering of multiple processing tools is another step in the development of low-thermal-budget, in situ, single-wafer processing. Such cluster tools require the development of well-controlled high throughput technologies that are cost effective and compatible with high-yield manufacturing.}, number={4}, journal={JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B}, author={MASNARI, NA}, year={1994}, pages={2749–2751} }
 @article{masnari_hauser_lucovsky_maher_markunas_ozturk_wortman_1993, title={CENTER FOR ADVANCED ELECTRONIC MATERIALS PROCESSING}, volume={81}, ISSN={["0018-9219"]}, DOI={10.1109/JPROC.1993.752025}, abstractNote={Microelectronics manufacturing technology is rapidly moving toward integrated circuits with submicron minimum feature sizes. This is being driven by the development of devices and circuits with reduced device lateral dimensions, increased density per chip, thinner material layers, increased use of the vertical dimension (three-dimensional circuits), low volume/fast tumaround design (ASIC's), increased use of heterojunctions, mixed material technologies, and quantum-based device structures. These trends require precise control of thin layers processed on wafers and a need for lower temperature processing or a lower overall thermal budget}, number={1}, journal={PROCEEDINGS OF THE IEEE}, author={MASNARI, NA and HAUSER, JR and LUCOVSKY, G and MAHER, DM and MARKUNAS, RJ and OZTURK, MC and WORTMAN, JJ}, year={1993}, month={Jan}, pages={42–59} }