@article{zhu_yelten_steer_franzon_2013, title={Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models}, volume={197}, ISBN={["978-3-642-34335-3"]}, ISSN={["2194-5365"]}, DOI={10.1007/978-3-642-34336-0_17}, abstractNote={This paper presents surrogate model-based methods to generate circuit performance models, device models, and high-speed IO buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. A new variation-aware IO buffer macromodel is developed by integrating surrogate modeling and a physically-based model structure. The new IO model provides both good accuracy and scalability for signal integrity analysis.}, journal={SIMULATION AND MODELING METHODOLOGIES, TECHNOLOGIES AND APPLICATIONS}, author={Zhu, Ting and Yelten, Mustafa Berke and Steer, Michael B. and Franzon, Paul D.}, year={2013}, pages={255–269} }
 @article{yelten_franzon_steer_2012, title={Analog Negative-Bias-Temperature-Instability Monitoring Circuit}, volume={12}, ISSN={["1558-2574"]}, DOI={10.1109/tdmr.2011.2178096}, abstractNote={A negative-bias-temperature-instability (NBTI) monitor subcircuit is presented and implemented in 65-nm CMOS technology. The subcircuit can be incorporated in various analog circuit blocks subject to different variability, stress, and aging histories. For an amplifier block, the NBTI monitor is a linear sensor, and sensing is provided as variation of the amplifier gain in response to NBTI-induced bias variation. The monitor sensitivity in this configuration is 3.15 V-1 and is demonstrated through electrothermal stress on the amplifier circuit.}, number={1}, journal={IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY}, author={Yelten, Mustafa Berke and Franzon, Paul D. and Steer, Michael B.}, year={2012}, month={Mar}, pages={177–179} }
 @article{yelten_franzon_steer_2012, title={Comparison of modeling techniques in circuit variability analysis}, volume={25}, ISSN={["1099-1204"]}, DOI={10.1002/jnm.836}, abstractNote={SUMMARY}, number={3}, journal={INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS}, author={Yelten, Mustafa Berke and Franzon, Paul D. and Steer, Michael B.}, year={2012}, pages={288–302} }
 @inproceedings{yelten_franzon_steer_2012, title={Process mismatch analysis based on reduced-order models}, DOI={10.1109/isqed.2012.6187561}, abstractNote={This paper describes a methodology based on reduced-order models to investigate the effects of process mismatch in analog circuits in the presence of reliability degradation. Neural network-based reduced-order models for the DC drain current, Ids, of 65 nm n- and p-channel transistors have been generated in terms of six process parameters, temperature, and device age. The models identify the contribution of process parameters to the mismatch of n- and p-channel transistors as they age. Hot carrier injection (HCI) is considered as the main reliability degradation for n-channel devices and negative bias temperature instability (NBTI) is considered for p-channel devices. It is demonstrated that the variations of the effective channel length and intrinsic threshold voltage are major contributors to device mismatch in the absence of aging. Finally, a beta multiplier current reference is analyzed using the developed models for the impact of process mismatch with and without the aging effects. It is shown that in a cascode current mirror the variability of the reference current can be reduced by ensuring that the same rail transistors experience similar variations.}, booktitle={2012 13th international symposium on quality electronic design (isqed)}, author={Yelten, M. B. and Franzon, Paul and Steer, M. B.}, year={2012}, pages={648–655} }
 @inproceedings{yelten_gard_2009, title={Theoretical analysis and characterization of the tunable matching networks in low noise amplifiers}, booktitle={2009 European Conference on Circuit Theory and Design, vols 1 and 2}, author={Yelten, M. B. and Gard, K. G.}, year={2009}, pages={890–893} }
 @article{yelten_franzon_steer, title={Surrogate-model-based analysis of analog circuits-part I: Variability analysis}, volume={11}, number={3}, journal={IEEE Transactions on Device and Materials Reliability}, author={Yelten, M. B. and Franzon, P. D. and Steer, M. B.}, pages={466–473} }
 @article{yelten_franzon_steer, title={Surrogate-model-based analysis of analog circuits-part II: Reliability analysis}, volume={11}, number={3}, journal={IEEE Transactions on Device and Materials Reliability}, author={Yelten, M. B. and Franzon, P. D. and Steer, M. B.}, pages={458–465} }