Nyunyi Marcus Tshibangu

Works (1)

Updated: April 11th, 2023 10:13

2013 conference paper

Design of controller for L2 cache mapped in Tezzaron stacked DRAM

2013 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA.

By: N. Tshibangu n, P. Franzon n , E. Rotenberg n & W. Davis n 

topics (OpenAlex): Parallel Computing and Optimization Techniques; Interconnection Networks and Systems; Advanced Data Storage Technologies
TL;DR: This paper investigates the implementation of such a cache controller using 3-layer 256 MB Tezzaron Octopus stacked DRAM, which provides a fast data access through burst-4 and burst-8 mode and has a low hit latency. (via Semantic Scholar)
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Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

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