@article{ramanan_lee_misra_2016, title={Physical understanding of trends in current collapse with atomic layer deposited dielectrics in AlGaN/GaN MOS heterojunction FETs}, volume={31}, ISSN={["1361-6641"]}, DOI={10.1088/0268-1242/31/3/035016}, abstractNote={Many passivation dielectrics are pursued for suppressing current collapse due to trapping/detrapping of access-region surface traps in AlGaN/GaN based metal oxide semiconductor heterojuction field effect transistors (MOS-HFETs). The suppression of current collapse can potentially be achieved either by reducing the interaction of surface traps with the gate via surface leakage current reduction, or by eliminating surface traps that can interact with the gate. But, the latter is undesirable since a high density of surface donor traps is required to sustain a high 2D electron gas density at the AlGaN/GaN heterointerface and provide a low ON-resistance. This presents a practical trade-off wherein a passivation dielectric with the optimal surface trap characteristics and minimal surface leakage is to be chosen. In this work, we compare MOS-HFETs fabricated with popular ALD gate/passivation dielectrics like SiO2, Al2O3, HfO2 and HfAlO along with an additional thick plasma-enhanced chemical vapor deposition SiO2 passivation. It is found that after annealing in N2 at 700 °C, the stack containing ALD HfAlO provides a combination of low surface leakage and a high density of shallow donor traps. Physics-based TCAD simulations confirm that this combination of properties helps quick de-trapping and minimal current collapse along with a low ON resistance.}, number={3}, journal={SEMICONDUCTOR SCIENCE AND TECHNOLOGY}, author={Ramanan, Narayanan and Lee, Bongmook and Misra, Veena}, year={2016}, month={Mar} }
 @article{ramanan_lee_misra_2015, title={ALD gate dielectrics for improved threshold voltage stability in AlGaN/GaN MOS-HFETs for power applications}, volume={30}, ISSN={["1361-6641"]}, DOI={10.1088/0268-1242/30/12/125017}, abstractNote={Dielectrics by atomic layer deposition (ALD) are sought after for fabricating AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors (MOS-HFETs) for power applications. The ideal gate dielectric is required to suppress gate leakage and minimize threshold voltage (VT) instability by hosting minimal interface traps. Additionally, with the need for an enhancement mode device, it is preferable if it minimizes VT shift in the negative direction. For the first time, we compare popular ALD dielectrics like SiO2, Al2O3, HfO2 and HfAlO with identical electrical thickness on AlGaN/GaN, thereby ensuring identical electrostatic conditions across different dielectrics. High-k ALD dielectrics (HfAlO, HfO2 and Al2O3) are found to suppress gate leakage but host a high density of interface traps with AlGaN, thereby resulting in significant VT instability. ALD SiO2 gate dielectric, annealed in N2 above 600 °C, is a promising gate dielectric candidate which provides the most stable and least negative shift in VT while also substantially suppressing gate leakage below that of an HFET.}, number={12}, journal={SEMICONDUCTOR SCIENCE AND TECHNOLOGY}, author={Ramanan, Narayanan and Lee, Bongmook and Misra, Veena}, year={2015}, month={Dec} }
 @article{ramanan_lee_misra_2015, title={Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory}, volume={106}, ISSN={0003-6951 1077-3118}, url={http://dx.doi.org/10.1063/1.4922799}, DOI={10.1063/1.4922799}, abstractNote={Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps with a variety of ALD dielectrics. High-k dielectrics (HfO2, HfAlO, and Al2O3) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO2 shows the lowest interface trap density (<2 × 1012 cm−2) after annealing above 600 °C in N2 for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.}, number={24}, journal={Applied Physics Letters}, publisher={AIP Publishing}, author={Ramanan, Narayanan and Lee, Bongmook and Misra, Veena}, year={2015}, month={Jun}, pages={243503} }
 @article{ramanan_lee_misra_2015, title={Comparison of Methods for Accurate Characterization of Interface Traps in GaN MOS-HFET Devices}, volume={62}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2014.2382677}, abstractNote={Reliability of dielectrics is a critical concern in GaN metal-oxide-semiconductor-heterojunction-field-effect transistor (MOS-HFET) devices for use in high-voltage power and RF applications. Accurate characterization of interface traps is essential toward developing an understanding of the reliability issues associated with this system and to evaluate the effectiveness of different dielectrics proposed for use in the gate-stack or the passivation of the access regions. Using small-signal equivalent circuit models and TCAD simulations, it is found that conductance and capacitance methods for trap density estimation potentially have severely constrained detection limits and can probe only shallow traps. In contrast, a pulsed-IV method, used along with UV irradiation, can accurately detect a wide range of trap densities over the entire wide bandgap. The effectiveness of this method is also experimentally demonstrated using an AlGaN/GaN MOS-HFET device with HfAlO gate dielectric.}, number={2}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ramanan, Narayanan and Lee, Bongmook and Misra, Veena}, year={2015}, month={Feb}, pages={546–553} }
 @inproceedings{ramanan_lee_misra_2014, title={A novel methodology using pulsed-IV for interface or border traps characterization on AlGaN/GaN MOSHFETs}, DOI={10.1109/ispsd.2014.6856052}, abstractNote={Characterization of traps at a dielectric/AlGaN interface is critical to evaluate the reliability of the dielectric for the gate stack or passivation of an AlGaN/GaN based MOS Heterojunction Field Effect Transistor (MOSHFET). In this work, we propose a new methodology for interface and border traps characterization using simple DC IV, CV and pulsed-IV measurements. Along with a generic UV lamp, we use this technique to characterize both shallow and deep trap concentrations across the entire AlGaN band gap. The resulting analysis of the ALD HfAlO/AlGaN interface reveals a high density of shallow traps (~7×10<sup>13</sup> cm<sup>-2</sup>.eV<sup>-1</sup>) and deep traps (10<sup>11</sup>-10<sup>12</sup> cm<sup>-2</sup>.eV<sup>-1</sup>) with a characteristic U-shape.}, booktitle={Proceedings of the international symposium on power semiconductor}, author={Ramanan, N. and Lee, B. and Misra, Veena}, year={2014}, pages={366–369} }
 @article{ramanan_lee_misra_2014, title={Device Modeling for Understanding AlGaN/GaN HEMT Gate-Lag}, volume={61}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2014.2313814}, abstractNote={Using a simple simulation framework, it is shown that a passivation dielectric that minimizes surface leakage and creates a high density of shallow traps at the surface is vital to minimize the formation of the virtual gate and eliminate AlGaN/GaN HEMT gate-lag. Under large negative gate voltage, this is also expected to create higher fields and current crowding at the gate edge, promoting an increase in total gate leakage. While the AlGaN barrier properties are also found to impact gate-lag, the use of a passivation dielectric that minimizes surface leakage can overpower it's influence and suppress current collapse. Access region shrinking and the use of a longer gate are also found to improve gate-lag.}, number={6}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ramanan, Narayanan and Lee, Bongmook and Misra, Veena}, year={2014}, month={Jun}, pages={2012–2018} }
 @article{sarkar_ramanan_jayanti_di spigna_lee_franzon_misra_2014, title={Dual Floating Gate Unified Memory MOSFET With Simultaneous Dynamic and Non-Volatile Operation}, volume={35}, ISSN={["1558-0563"]}, DOI={10.1109/led.2013.2289751}, abstractNote={Dual floating gate flash memory has been fabricated and characterized to show dynamic operation, non-volatile operation, and simultaneous dynamic and non-volatile operation. The gate stack consists of a thin dielectric separating two floating gates sandwiched between a tunnel dielectric and interpoly dielectric. The quality of the thin dielectric that separates the floating gates is of utmost importance to retain dynamic operation. In this letter, we investigate a dual floating gate memory transistor and show its potential to combine DRAM and flash functionality in the same device.}, number={1}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Sarkar, Biplab and Ramanan, Narayanan and Jayanti, Srikant and Di Spigna, Neil and Lee, Bongmook and Franzon, Paul and Misra, Veena}, year={2014}, month={Jan}, pages={48–50} }
 @article{kirkpatrick_lee_ramanan_misra_2014, title={Flash MOS-HFET operational stability for power converter circuits}, volume={11}, ISSN={["1862-6351"]}, DOI={10.1002/pssc.201300547}, abstractNote={Abstract}, number={3-4}, journal={PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 11, NO 3-4}, author={Kirkpatrick, Casey and Lee, Bongmook and Ramanan, Narayanan and Misra, Veena}, year={2014}, pages={875–878} }
 @article{ramanan_lee_kirkpatrick_suri_misra_2013, title={Properties of atomic layer deposited dielectrics for AlGaN/GaN device passivation}, volume={28}, ISSN={["1361-6641"]}, DOI={10.1088/0268-1242/28/7/074004}, abstractNote={In order to minimize ac–dc dispersion, reduce gate leakage and maximize ac transconductance, there is a critical need to identify optimal interfaces, low-k passivation dielectrics and high-k gate dielectrics. In this paper, an investigation of different atomic layer deposited (ALD) passivation dielectrics on AlGaN/GaN-based hetero-junction field effect transistors (HFETs) was performed. Angle-resolved x-ray photoelectron spectroscopy revealed that HCl/HF and NH4OH cleans resulted in a reduction of native oxide and carbon levels at the GaN surface. The role of high temperature anneals, following the ALD, on the effectiveness of passivation was also explored. Gate-lag measurements on HFETs passivated with a thin ALD high-k Al2O3 or HfAlO layer capped with a thick plasma enhanced chemical vapor deposited (PECVD) low-k SiO2 layer, annealed at 600–700 °C, were found to be as good as or even better than those with conventional PECVD silicon nitride passivation. Further, it was observed that different passivation dielectric stacks required different anneal temperatures for improved gate-lag behavior compared to the as-deposited case.}, number={7}, journal={SEMICONDUCTOR SCIENCE AND TECHNOLOGY}, author={Ramanan, Narayanan and Lee, Bongmook and Kirkpatrick, Casey and Suri, Rahul and Misra, Veena}, year={2013}, month={Jul} }
 @article{ramanan_misra_2011, title={Multivalued Logic Using a Novel Multichannel GaN MOS Structure}, volume={32}, ISSN={["1558-0563"]}, DOI={10.1109/led.2011.2163149}, abstractNote={Bulk-Si CMOS technology has been consistently improving for over 40 years, following Moore's law, by gate length scaling. In this letter, we present a novel charge-based multistate transistor device on the AlGaN/GaN system which uses a given gate length but handles more than two states any time. This novel multichannel MOS device, having a higher processing capability than a binary transistor, is then used to implement multiple valued logic gates in a pull-down network scheme. In this letter, we use the results of a 2-D device simulation as proof of concept and propose architectures for the implementation of some basic quaternary logic gates.}, number={10}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Ramanan, Narayanan and Misra, Veena}, year={2011}, month={Oct}, pages={1379–1381} }