Onkar Patil

Works (4)

Updated: July 5th, 2023 15:05

2020 conference paper

Symbiotic HW Cache and SW DTLB Prefetching for DRAM/NVM Hybrid Memory

2020 28th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 1–8.

By: O. Patil n, F. Mueller n, L. Ionkov *, J. Lee * & M. Lang *

TL;DR: It is hypothesized that HW and SW prefetching can complement each other in placing data in caches and the Data Translation Look-aside Buffer (DTLB) prior to their references, and by doing so adaptively, highly varying access latencies in a DRAM/NVM hybrid memory system are taken into account. (via Semantic Scholar)
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Added: February 1, 2021

2019 article

End-to-End Resilience for HPC Applications

HIGH PERFORMANCE COMPUTING, ISC HIGH PERFORMANCE 2019, Vol. 11501, pp. 271–290.

By: A. Rezaei  n, H. Khetawat n, O. Patil n, F. Mueller n, P. Hargrove * & E. Roman*

author keywords: Resilience; Silent data corruption; Pragma programming
TL;DR: The live vulnerability factor (LVF) is introduced, a new metric that quantifies any lack of end-to-end protection for a given data structure that lifts the data protection burden from application programmers allowing them to focus solely on algorithms and performance while resilience is specified and subsequently embedded into the code through the compiler/library and supported by the runtime system. (via Semantic Scholar)
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Added: November 18, 2019

2019 conference paper

Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules

Proceedings of the International Symposium on Memory Systems - MEMSYS '19. Presented at the the International Symposium.

By: O. Patil n, L. Ionkov *, J. Lee *, F. Mueller n & M. Lang *

author keywords: NVM; Persistent Memory; Intel Optane DC; Memory Allocation; Hybrid Memory; NUMA; SICM
TL;DR: It is found that Optane-only executions are slower in terms of execution time than DRAM-only and Memory-mode executions by a minimum of 2 to 16% for VPIC and maximum of 6x for LULESH, which means HPC mini-apps can now scale up the their problem size given such a memory system. (via Semantic Scholar)
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7. Affordable and Clean Energy (OpenAlex)
Source: Crossref
Added: March 2, 2020

2016 conference paper

Efficient and predictable group communication for manycore NoCs

High performance computing, 9697, 383–403.

By: K. Yagna, O. Patil & F. Mueller

Source: NC State University Libraries
Added: August 6, 2018

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