Carlton M. Osburn

Frontend processes required for continued CMOS scaling

Solid State Technology, 49(2), 46-.

Effect of post-metallization annealing for alternative gate stack devices

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 151(2), F29–F35.

Stability of advanced gate stack devices

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 151(2), F22–F28.

Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 46(2-3), 299–315.

The technical community in the 21st century

Informacije Midem = Journal of Microelectronics, Electronic Components and Materials, 69(1), 37.

Design and integration considerations for end-of-the roadmap ultrashallow junctions

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, Vol. 18, pp. 338–345.

Impact of gate workfunction on device performance at the 50 nm technology node

SOLID-STATE ELECTRONICS, 44(6), 1077–1080.

Limitations of the modified shift-and-ratio technique for extraction of the bias dependence of L-eff and R-sd of LDD MOSFET's

IEEE TRANSACTIONS ON ELECTRON DEVICES, 47(4), 891–895.

Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices

IEEE TRANSACTIONS ON ELECTRON DEVICES, 46(8), 1711–1717.

Lateral gettering of Fe on bulk and silicon-on-insulator wafers

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 146(5), 1925–1928.

Elevated n(+)/p junctions by implant into CoSi2 formed on selective epitaxy for deep submicron MOSFET's

IEEE TRANSACTIONS ON ELECTRON DEVICES, 45(9), 1946–1952.

Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs

RAPID THERMAL AND INTEGRATED PROCESSING VII, Vol. 525, pp. 163–170.

Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics

IEEE TRANSACTIONS ON ELECTRON DEVICES, 45(6), 1377–1380.

Low parasitic resistance contacts for scaled ULSI devices

Osburn, C. M., & Bellur, K. R. (1998, November 2). THIN SOLID FILMS, Vol. 332, pp. 428–436.

Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 145(6), 2131–2137.

Techniques and applications of secondary ion mass spectrometry and spreading resistance profiling to measure ultrashallow junction implants down to 0.5 keV B and BF2

Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures, 16(1), 286–291.

A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy

ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 571–585. Pennington, NJ: Electrochemical Society.

A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 144(10), 3659–3664.

Dose-rate effects on the formation of ultra-shallow junctions with low-energy B+ and BF2+ ion implants

Downey, D. F., Osburn, C. M., Cummings, J. J., Daryanani, S., & Falk, S. W. (1997, October 31). THIN SOLID FILMS, Vol. 308, pp. 562–569.

Effects of silicon layer properties on device reliability for 0.1-μm SOI n-MOSFET design strategies

IEEE Transactions on Electron Devices, 44(5), 815–821.

Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology

ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 587–597. Pennington, NJ: Electrochemical Society.

The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's

IEEE TRANSACTIONS ON ELECTRON DEVICES, 44(9), 1491–1498.

The impact of in-situ rapid thermal gate dielectric processes on deep submicron MOSFETs

SOLID-STATE ELECTRONICS, 41(4), 619–625.

Ultrashallow junction formation by ion implant and RTA

Solid State Technology, 40(12), 71.

Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition

RAPID THERMAL AND INTEGRATED PROCESSING V, Vol. 429, pp. 343–347.