@article{butterbaugh_osborn_2006, title={Frontend processes required for continued CMOS scaling}, volume={49}, number={2}, journal={Solid State Technology}, author={Butterbaugh, J. and Osborn, C.}, year={2006}, pages={46-} }
 @article{kim_han_osburn_2004, title={Effect of post-metallization annealing for alternative gate stack devices}, volume={151}, ISSN={["1945-7111"]}, DOI={10.1149/1.1636181}, abstractNote={The effect of the post-metallization annealing of devices having HfO 2 , La 2 O 3 , or Y 2 O 3 dielectrics and poly-Si or TaN gate electrodes was studied. Forming gas (10% H 2 /90% N 2 ) annealing at 400°C enhanced drive current and channel mobility of devices having 1.2 nm HfO 2 gate dielectrics, by eliminating interface states. Post-metal annealing in 10% D 2 for 1.2 nm HfO 2 gate dielectrics resulted in larger enhancements in drive current and device channel mobility than forming gas annealing. Similar enhancements of the device characteristics were observed in La 2 O 3 (300 mV shift in both flatband and threshold voltage) and Y 2 O 3 (200 mV shift only in threshold voltage) materials. Annealing in pure nitrogen was found to degrade the dielectric quality of HfO 2 , including a decrease in device current and 50% lower capacitance.}, number={2}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Kim, I and Han, SK and Osburn, CM}, year={2004}, month={Feb}, pages={F29–F35} }
 @article{kim_han_osburn_2004, title={Stability of advanced gate stack devices}, volume={151}, ISSN={["1945-7111"]}, DOI={10.1149/1.1636180}, abstractNote={The stability of poly-Si gated HfO 2 (∼1.2 nm equivalent oxide thickness, EOT) and Y 2 O 3 (∼3.1 nm EOT) n-channel metal oxide semiconductor field effect transistor devices were assessed after constant current stressing of the gate. The changes in threshold voltage and transconductance were measured as a function of stress time and stress current over the range of 10 -3 to 10 5 C of injected charge per square centimeter. With forming gas annealed HfO 2 , positive shifts in the threshold voltage exhibited a power-law dependence. Under high stressing conditions, a power-law dependence of degradation of threshold voltage on the injected charge (∼Q 0.1 ) was observed. Stressing at high current was seen to generate traps. Stressing at low current revealed a saturation of the threshold voltage after modest stressing times. Stressing on deuterium annealed sample showed less V t and g m shift (under high injection conditions), which is attributed to the effectiveness of heavier D 2 in preventing trap generation under high stressing conditions. With Y 2 O 3 , stressed at similar electric fields, the threshold voltage shifted negatively and the transconductance increased.}, number={2}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Kim, I and Han, SK and Osburn, CM}, year={2004}, month={Feb}, pages={F22–F28} }
 @article{osburn_kim_han_de_yee_gannavaram_lee_lee_luo_zhu_et al._2002, title={Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?}, volume={46}, ISSN={["2151-8556"]}, DOI={10.1147/rd.462.0299}, abstractNote={The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO2 in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT)-for example, HfO2, ZrO2, and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (∼105 A/cm2). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and annealing processes can certainly be extended to meet the junction-depth and series-resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.}, number={2-3}, journal={IBM JOURNAL OF RESEARCH AND DEVELOPMENT}, author={Osburn, CM and Kim, I and Han, SK and De, I and Yee, KF and Gannavaram, S and Lee, SJ and Lee, CH and Luo, ZJ and Zhu, W and et al.}, year={2002}, pages={299–315} }
 @article{osburn_2001, title={The technical community in the 21st century}, volume={69}, number={1}, journal={Informacije Midem = Journal of Microelectronics, Electronic Components and Materials}, author={Osburn, C. M.}, year={2001}, pages={37} }
 @article{osburn_de_yee_srivastava_2000, title={Design and integration considerations for end-of-the roadmap ultrashallow junctions}, volume={18}, ISSN={["1071-1023"]}, DOI={10.1116/1.591195}, abstractNote={Device simulations and response surface analysis have been used to quantify the trade-offs and issues encountered in designing ultrashallow junctions for the 250–50 nm generations of complimentary metal-oxide-semiconductor ultralarge scale integration technology. The design of contacting and extension junctions is performed to optimize short channel effects, performance, and reliability, while meeting the National Technology Roadmap for Semiconductors off-state leakage specifications. A maxima in saturated drive current is observed for an intermediate extension junction depth (∼20 nm for 100 nm technology): shallower junctions lead to higher series resistance, and deeper junctions result in more severe short channel effects. The gate-to-junction overlap required to preserve drive current was seen to depend on junction abruptness. For a perfectly abrupt junction, it is not necessary for the gate to overlap the junction. Performance depends on many parameters, including: overlap of gate to extension junction, junction capacitance, and parasitic series resistance, which depends on the doping gradient at the junction (spreading resistance), the extension series resistance, and the contact resistance. Extraction of these parameters using I–V or C–V measurements can potentially lead to erroneous conclusions about lateral junction excursion and abruptness.}, number={1}, journal={JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B}, author={Osburn, CM and De, I and Yee, KF and Srivastava, A}, year={2000}, pages={338–345} }
 @article{de_johri_srivastava_osburn_2000, title={Impact of gate workfunction on device performance at the 50 nm technology node}, volume={44}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(99)00323-8}, abstractNote={The optimal gate electrode workfunction was determined for the 50 nm technology node using a simulation strategy that takes into account the impact of short-channel effects on device performance in uniformly doped and super-steep-retrograde doped channels in conventional and dynamic threshold operation. Classical device simulations suggest that the optimal workfunction is such that the gate Fermi level is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS) devices. However, when quantum mechanical effects are taken into account, the optimal workfunction is such that the gate Fermi level coincides with the conduction (valence) band edge. Midgap gates are not viable because the resulting short-channel effects are too severe. In a surrounding-gate transistor the optimal workfunction is attained when the gate Fermi level is 0.35 eV below (above) the conduction (valence) band edge in NMOS (PMOS) device. Midgap gates are not viable because the resulting threshold voltage is too high and cannot be reduced by lowering the substrate doping.}, number={6}, journal={SOLID-STATE ELECTRONICS}, author={De, I and Johri, D and Srivastava, A and Osburn, CM}, year={2000}, month={Jun}, pages={1077–1080} }
 @article{ahmed_de_osburn_wortman_hauser_2000, title={Limitations of the modified shift-and-ratio technique for extraction of the bias dependence of L-eff and R-sd of LDD MOSFET's}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.831010}, abstractNote={The purpose of this study, based on two-dimensional (2-D) simulation, was to scale effective channel length and series resistance extraction routines for sub-100 nm CMOS devices. We demonstrate that L/sub eff/- and R/sub sd/-gate-bias dependence extracted using a modified shift-and-ratio (M-S&R) method may not give accurate results because of a nonnegligible effective mobility dependence on gate bias. Using a reasonable gate bias-dependent mobility model, one observes a finite V/sub g/ dependence of L/sub eff/ and R/sub sd/ even for devices with degenerately doped drain junction.}, number={4}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and De, I and Osburn, C and Wortman, J and Hauser, J}, year={2000}, month={Apr}, pages={891–895} }
 @article{de_osburn_1999, title={Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices}, volume={46}, ISSN={["0018-9383"]}, DOI={10.1109/16.777161}, abstractNote={Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node, according to the scheme targeted by the National Technology Roadmap for Semiconductors (1997). The comparison was done at the same gate length L/sub gate/ and the same off-state leakage current I/sub off/, where it was found that SSR profiles always have higher threshold voltages, poorer subthreshold swings, higher linear currents, and lower saturation currents than UD profiles. Using a simulation strategy that takes into account the impact of short-channel effects on drive current, it was found that the improved short-channel effect of retrograde profiles is not enough to translate into a higher performance over the UD channels for all technologies. Hence, if the effective gate-dielectric thickness scales linearly with technology, retrograde doping will not be useful from a performance point of view. However, if the scaling of the gate-dielectric is limited to about 2 nm, SSR profiles can give higher drive current than UD channels for the end of the roadmap devices. Thus, the suitability of SSR channels over UD channels depends on the gate-dielectric scaling strategy. Simulations using a self-consistent Schrodinger-Poisson solver were also used to show that the impact of quantum mechanical (QM) effects on the long-channel characteristics of SSR and UD MOSFET's will be similar.}, number={8}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={De, I and Osburn, CM}, year={1999}, month={Aug}, pages={1711–1717} }
 @article{beaman_kononchuk_koveshnikov_osburn_rozgonyi_1999, title={Lateral gettering of Fe on bulk and silicon-on-insulator wafers}, volume={146}, ISSN={["1945-7111"]}, DOI={10.1149/1.1391867}, abstractNote={Laterally displaced gettering sites have been studied as an alternative to traditional internal gettering and back-side gettering sites. Fe was diffused laterally and captured, first by coulombic pairing with B in p-type Si, and then by strategically placed ion implantation induced dislocation loops. This localization of Fe was tracked by both deep level transient spectroscopy and capacitance-voltage measurements. As proof of the viability of the gettering technique, laterally displaced gettering sites were formed adjacent to capacitors on various silicon-on-insulator (SOI) substrate types. Both implantation induced dislocation loops and P diffusion were used for gettering. An improvement in gate oxide integrity was observed for capacitors with lateral gettering on all SOI types studied.}, number={5}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Beaman, KL and Kononchuk, O and Koveshnikov, S and Osburn, CM and Rozgonyi, GA}, year={1999}, month={May}, pages={1925–1928} }
 @article{sun_tsai_osburn_1998, title={Elevated n(+)/p junctions by implant into CoSi2 formed on selective epitaxy for deep submicron MOSFET's}, volume={45}, ISSN={["0018-9383"]}, DOI={10.1109/16.711360}, abstractNote={Very shallow elevated n/sup +//p junctions formed by arsenic implant into or through cobalt silicide (CoSi/sub 2/) formed on selective epitaxial layers and their application to deep submicron n-channel MOSFETs were studied for the first time. PREDICT 1.6 simulation program was employed to choose the desired implant energies and annealing thermal cycle based on theoretically predicted silicide thickness. The implanted CoSi/sub 2/ elevated junctions had low reverse current and no bias voltage dependence up to 5 V. Diffusion current dominated the junction forward current, and good ideality factors close to 1 were obtained. A nearly abrupt junction doping profile was achieved. Deep submicron n-channel MOSFETs incorporating implanted CoSi/sub 2/ elevated junctions were demonstrated. Sharp turn-off and reasonably large drain currents were achieved.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sun, JJ and Tsai, JY and Osburn, CM}, year={1998}, month={Sep}, pages={1946–1952} }
 @article{srivastava_heinisch_vogel_parker_osburn_masnari_wortman_hauser_1998, title={Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs}, volume={525}, ISBN={["1-55899-431-9"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-525-163}, abstractNote={ABSTRACT}, journal={RAPID THERMAL AND INTEGRATED PROCESSING VII}, author={Srivastava, A and Heinisch, HH and Vogel, E and Parker, C and Osburn, CM and Masnari, NA and Wortman, JJ and Hauser, JR}, year={1998}, pages={163–170} }
 @article{sun_osburn_1998, title={Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics}, volume={45}, ISSN={["0018-9383"]}, DOI={10.1109/16.678583}, abstractNote={Deep submicron elevated source/drain (S/D) MOSFET's with epi facets, without facets, and with a second sidewall spacer covering the facets were studied using two-dimensional (2-D) process and device simulations. A slight degradation of drain-induced-barrier-lowering /spl Delta/V/sub t/ (DIBL) has been projected due to the locally deeper junction beneath the epi facets. The locally deeper junction also shortens the S/D extension length if the spacer thickness is kept the same. The shorter extension in turn leads to a smaller parasitic resistance and therefore a higher device drive current. Gate-to-drain capacitance of the elevated S/D MOSFET is decreased as a result of faceting because of the reduced overlap area.}, number={6}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sun, JJ and Osburn, CM}, year={1998}, month={Jun}, pages={1377–1380} }
 @article{osburn_bellur_1998, title={Low parasitic resistance contacts for scaled ULSI devices}, volume={332}, ISSN={["0040-6090"]}, DOI={10.1016/S0040-6090(98)01046-3}, abstractNote={Analysis of the components of parasitic series resistance in ULSI devices shows that interfacial contact resistivities less than 10−7 Ω cm2 will be required for sub 100-nm ULSI devices in order to stay on the historical performance trend. With dimensional scaling, the series resistance–width product decreases because channel lengths are scaled, while it increases in contacts because the contact length is decreased. Unless the contact resistivity is also reduced, the contact resistance ultimately becomes higher than the channel resistance, and no performance advantage will be obtained by making the device smaller. The challenge in meeting the contacting requirements in the 1997 National Technology Roadmap for Semiconductors is especially difficult in light of the desire to simultaneously contact both n+ and p+ junctions with a single material and given the trend towards lower processing temperatures, in which the equilibrium dopant electrical activity is lower. Several techniques, such as dielectric capping during junction annealing, are effective in reducing contact resistivity by maximizing interfacial dopant concentrations and minimizing contact barrier heights. Higher saturated drive currents, due to lowered parasitic series resistance, are observed in deep submicron devices made using silicides as diffusion sources (SADS); this technique eliminates the interfacial dopant segregation that is associated with conventional silicidation. The use of elevated source drains (ESD) also allows the use of thicker silicides while minimizing the consumption-induced increase in contact resistivity that normally accompanies silicidation; as a result, ESD devices give higher drive currents. The recrystallization of amorphous layers has been observed to result in non-equilibrium dopant activation which can be many times the equilibrium value. Finally, the use of heterojunction contacts using Si–Ge in the context of elevated source/drain devices presents another way to achieve lower contact resistance.}, number={1-2}, journal={THIN SOLID FILMS}, author={Osburn, CM and Bellur, KR}, year={1998}, month={Nov}, pages={428–436} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1998, title={Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors}, volume={145}, ISSN={["1945-7111"]}, DOI={10.1149/1.1838607}, abstractNote={Device drive current, parasitic resistance, and junction leakage current have been studied using silicided and non-silicided deep submicron elevated source/drain (ESD) n-channel metal oxide semiconductor field effect transistors (NMOSFETs). This study illustrated the effects of doping profile in the elevated S/D region, junction depth in the substrate, and doping level in the source/drain extension. Compared to devices having nonelevated junctions with the same substrate doping profile, MOSFETs with a profile-doped elevated S/D, used to contact an ultrashallow junction formed before selective epitaxial growth, had higher drive currents and demonstrated the ability of the elevated junction to reduce the extrinsic resistance. Measurements of drive currents in ESD devices showed that (i) the lightly doped region at the bottom of a profile-doped elevated layer introduces additional extrinsic resistance, and (ii) the locally deeper junction beneath the epi facets extends laterally toward the channel and shortens the drain extension length, thereby reducing the intrinsic resistance. Silicided devices had higher drive current and reduced parasitic resistance when the silicide/silicon interfacial dopant concentrations remained high (>1 x 10 20 /cm 3 ) after silicidation. The lowest total parasitic resistance was achieved when the elevated S/D was used to give a small contact resistance to a shallow junction and a moderately doped drain extension was used to lower the resistance of the source/drain extension tab.}, number={6}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Sun, J and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA and Westhoff, R}, year={1998}, month={Jun}, pages={2131–2137} }
 @article{harrington_magee_pawlik_downey_osburn_felch_1998, title={Techniques and applications of secondary ion mass spectrometry and spreading resistance profiling to measure ultrashallow junction implants down to 0.5 keV B and BF2}, volume={16}, number={1}, journal={Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures}, author={Harrington, W. L. and Magee, C. W. and Pawlik, M. and Downey, D. F. and Osburn, C. M. and Felch, S. B.}, year={1998}, pages={286–291} }
 @inproceedings{srivastava_sun_bellur_bartholomew_o'neil_celik_osburn_masnari_ozturk_westhoff_et al._1997, title={A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy}, booktitle={ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3)}, publisher={Pennington, NJ: Electrochemical Society}, author={Srivastava, A. and Sun, J. and Bellur, K. and Bartholomew, R. F. and O'Neil, P. and Celik, S. M. and Osburn, C. M. and Masnari, N. A. and Ozturk, M. C. and Westhoff, R. and et al.}, year={1997}, pages={571–585} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1997, title={A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors}, volume={144}, ISSN={["1945-7111"]}, DOI={10.1149/1.1838066}, abstractNote={Ultrashallow elevated n'/p junctions (∼75 nm) incorporating selectively deposited epitaxial silicon layers were fabricated. The undoped epi layers (∼100 nm) were deposited on exposed diffusion areas in an Advanced Semiconductor Material Epsilon I system specifically designed for low thermal budget single-wafer processing. Shallow junctions (∼75 nm) were formed by ion implantation (As, 4 x 10 15 /cm 2 , 80 keV) into undoped epi layers and out-diffusion into the underlying substrate. Alternatively, an ion implanted (As, 4 x 10 15 /cm 2 , 60 keV) elevated layer was utilized to contact a shallow junction, which was formed (As, 1.5 x 10 15 /cm 2 , 15 keV) before the epi deposition. All junctions were annealed at 950°C for 10 s. Nonsilicided elevated junctions and conventional nonelevated (As, 1.5 x 10 15 /cm 2 , 15 keV) ones displayed very similar junction characteristics. Silicided nonelevated ultrashallow junctions, however, showed large reverse leakage current due to the substrate consumption. Both silicided elevated (post-epi and pre-epi) junctions exhibited excellent forward characteristics and low reverse leakage current. The difference in the reverse leakage characteristics of these two elevated junctions was attributed to the epi faceting formed at the sidewall edge of localized oxidation of silicon isolation. Deep submicron n = channel metal oxide semiconductor field effect transistors incorporating these junctions were also fabricated and electrically tested. Both elevated source/drain (S/D) devices show superior current driving capability compared to nonelevated ones as a result of much reduced parasitic resistance from contact source/drain junctions.}, number={10}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Sun, J and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA and Westhoff, R}, year={1997}, month={Oct}, pages={3659–3664} }
 @article{downey_osburn_cummings_daryanani_falk_1997, title={Dose-rate effects on the formation of ultra-shallow junctions with low-energy B+ and BF2+ ion implants}, volume={308}, ISSN={["1879-2731"]}, DOI={10.1016/S0040-6090(97)00494-X}, abstractNote={11B+ and 49BF2+ implants on a Varian VIISion-80 PLUS Ion Implanter from 2.0 to 8.9 keV at a dose of 1E15/cm2, and at various controlled and measured (in situ) peak beam-current densities, ranging from 3 to 600 μA/cm2, were investigated to study the effects of dose rate on the formation of ultra-shallow junctions. The implants and annealing conditions were chosen to produce junction depths, as measured by secondary ion mass spectrometry (SIMS), of 40 to 150 nm. In addition, a comprehensive study of B vs. BF2 at a boron effective energy of 2.0 keV (i.e. B at 2.0 keV and BF2 at 8.9 keV) was undertaken. The results show that for the implant conditions investigated the dose rate does not have a significant effect (if any) on the junction depth and that there is a distinct advantage to BF2 implants in forming shallower junctions. This advantage is not dose-rate related, but is related to the presence of fluorine. This paper also addresses the effects of pre-amorphization with Ge on dopant activation and on transient enhanced diffusion, and annealing techniques to optimize sheet resistance while minimizing junction depths. The background concentration of O2 during anneal was found to have a dramatic impact on the annealed junction (from oxidation-enhanced diffusion). Reducing the O2 concentration to trace amounts, produced the shallowest junctions observed. By combining those techniques which reduce boron diffusion, junctions that were only 39 nm deep, having a sheet resistance of 361 Ω/sq., were fabricated with 5 keV BF2.}, journal={THIN SOLID FILMS}, author={Downey, DF and Osburn, CM and Cummings, JJ and Daryanani, S and Falk, SW}, year={1997}, month={Oct}, pages={562–569} }
 @article{hulfachor_kim_littlejohn_osburn_1997, title={Effects of silicon layer properties on device reliability for 0.1-μm SOI n-MOSFET design strategies}, volume={44}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.568044}, DOI={10.1109/16.568044}, abstractNote={We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-/spl mu/m SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10/sup 16/ cm/sup -3/) channel and 2) a heavily-doped (10/sup 18/ cm/sup -3/) channel. For each design, the silicon layer thicknesses (T/sub Si/) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO/sub 2/ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T/sub Si/ results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead.}, number={5}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hulfachor, R.B. and Kim, K.W. and Littlejohn, M.A. and Osburn, C.M.}, year={1997}, month={May}, pages={815–821} }
 @inproceedings{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1997, title={Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology}, booktitle={ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3)}, publisher={Pennington, NJ: Electrochemical Society}, author={Sun, J. and Bartholomew, R. F. and Bellur, K. and Srivastava, A. and Osburn, C. M. and Masnari, N. A. and Westhoff, R.}, year={1997}, pages={587–597} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_1997, title={The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's}, volume={44}, ISSN={["0018-9383"]}, DOI={10.1109/16.622606}, abstractNote={Deep submicron NMOSFETs with elevated source/drain (ESD) were fabricated using self-aligned selective epitaxial deposition and engineered ion implanted profiles in the elevated layers, Deeper source/drain (S/D) junctions give rise to improved drive current over shallower profiles when the same spacer thickness and LDD doping level are used, Shallower junctions, especially with the heavily-doped S/D residing in the elevated layer, give better immunity to drain-induced-barrier lowering (DLBL) and bulk punchthrough. Tradeoffs between short-channel behavior and drive current with regard to S/D junction depth and spacer thickness were further studied using process/device simulations to cover a broader range of structure parameters. Despite the existence of epi facets along the sidewall spacers, the elevated S/D could be used as a sacrificial layer for silicidation, without degradation of the low-leakage junctions. The effects of the elevated S/D doping profile on substrate current and hot-electron-induced degradation were measured and analyzed. The simulated results were used, for the first time, to define the range of spacer thickness and LDD doses that are required in order for the lightly-doped region in the elevated S/D to effectively suppress the lateral electric field.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sun, JJ and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA}, year={1997}, month={Sep}, pages={1491–1498} }
 @article{zhang_osburn_1997, title={The impact of in-situ rapid thermal gate dielectric processes on deep submicron MOSFETs}, volume={41}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(96)00195-5}, abstractNote={Abstract High performance MOSFETs having effective channel lengths of 0.18 ± 0.06 μm were individually optimized and fabricated with four different gate dielectrics, including Furnace, rapid thermal oxides (RTO), rapid thermal chemical vapor deposited (RTCVD) and remote plasma enhanced chemical vapor deposited (RPECVD). The advantages of the shallower channel profiles offered by the low-thermal budget gate dielectric processes were identified through the design of channel doping profiles for the different gate dielectrics. Excellent device electrical characteristics were achieved for all four cases: Isat ∼ 410 μA μm−1; Ioff}, number={4}, journal={SOLID-STATE ELECTRONICS}, author={Zhang, KX and Osburn, CM}, year={1997}, month={Apr}, pages={619–625} }
 @article{downey_osburn_marcus_1997, title={Ultrashallow junction formation by ion implant and RTA}, volume={40}, number={12}, journal={Solid State Technology}, author={Downey, D. F. and Osburn, C. M. and Marcus, S. D.}, year={1997}, pages={71} }
 @article{sun_bartholomew_bellur_oneil_srivastava_violette_ozturk_osburn_masnari_1996, title={Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition}, volume={429}, ISBN={["1-55899-332-0"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-429-343}, abstractNote={Abstract}, journal={RAPID THERMAL AND INTEGRATED PROCESSING V}, author={Sun, J and Bartholomew, RF and Bellur, K and ONeil, PA and Srivastava, A and Violette, KE and Ozturk, MC and Osburn, CM and Masnari, NA}, year={1996}, pages={343–347} }