Carlton Osburn

Butterbaugh, J., & Osborn, C. (2006). Frontend processes required for continued CMOS scaling. Solid State Technology, 49(2), 46-.

Kim, I., Han, S. K., & Osburn, C. M. (2004). Effect of post-metallization annealing for alternative gate stack devices. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 151(2), F29–F35. https://doi.org/10.1149/1.1636181

Kim, I., Han, S. K., & Osburn, C. M. (2004). Stability of advanced gate stack devices. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 151(2), F22–F28. https://doi.org/10.1149/1.1636180

Osburn, C. M., Kim, I., Han, S. K., De, I., Yee, K. F., Gannavaram, S., … Ozturk, M. C. (2002). Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 46(2-3), 299–315. https://doi.org/10.1147/rd.462.0299

Osburn, C. M. (2001). The technical community in the 21st century. Informacije Midem = Journal of Microelectronics, Electronic Components and Materials, 69(1), 37.

Osburn, C. M., De, I., Yee, K. F., & Srivastava, A. (2000). Design and integration considerations for end-of-the roadmap ultrashallow junctions. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, Vol. 18, pp. 338–345. https://doi.org/10.1116/1.591195

De, I., Johri, D., Srivastava, A., & Osburn, C. M. (2000). Impact of gate workfunction on device performance at the 50 nm technology node. SOLID-STATE ELECTRONICS, 44(6), 1077–1080. https://doi.org/10.1016/S0038-1101(99)00323-8

Ahmed, K., De, I., Osburn, C., Wortman, J., & Hauser, J. (2000). Limitations of the modified shift-and-ratio technique for extraction of the bias dependence of L-eff and R-sd of LDD MOSFET's. IEEE TRANSACTIONS ON ELECTRON DEVICES, 47(4), 891–895. https://doi.org/10.1109/16.831010

De, I., & Osburn, C. M. (1999). Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices. IEEE TRANSACTIONS ON ELECTRON DEVICES, 46(8), 1711–1717. https://doi.org/10.1109/16.777161

Beaman, K. L., Kononchuk, O., Koveshnikov, S., Osburn, C. M., & Rozgonyi, G. A. (1999). Lateral gettering of Fe on bulk and silicon-on-insulator wafers. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 146(5), 1925–1928. https://doi.org/10.1149/1.1391867

Sun, J. J., Tsai, J. Y., & Osburn, C. M. (1998). Elevated n(+)/p junctions by implant into CoSi2 formed on selective epitaxy for deep submicron MOSFET's. IEEE TRANSACTIONS ON ELECTRON DEVICES, 45(9), 1946–1952. https://doi.org/10.1109/16.711360

Srivastava, A., Heinisch, H. H., Vogel, E., Parker, C., Osburn, C. M., Masnari, N. A., … Hauser, JR. (1998). Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs. RAPID THERMAL AND INTEGRATED PROCESSING VII, Vol. 525, pp. 163–170. https://doi.org/10.1557/proc-525-163

Sun, J. J., & Osburn, C. M. (1998). Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics. IEEE TRANSACTIONS ON ELECTRON DEVICES, 45(6), 1377–1380. https://doi.org/10.1109/16.678583

Osburn, C. M., & Bellur, K. R. (1998, November 2). Low parasitic resistance contacts for scaled ULSI devices. THIN SOLID FILMS, Vol. 332, pp. 428–436. https://doi.org/10.1016/S0040-6090(98)01046-3

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1998). Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 145(6), 2131–2137. https://doi.org/10.1149/1.1838607

Harrington, W. L., Magee, C. W., Pawlik, M., Downey, D. F., Osburn, C. M., & Felch, S. B. (1998). Techniques and applications of secondary ion mass spectrometry and spreading resistance profiling to measure ultrashallow junction implants down to 0.5 keV B and BF2. Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures, 16(1), 286–291.

Srivastava, A., Sun, J., Bellur, K., Bartholomew, R. F., O'Neil, P., Celik, S. M., … Fowler, B. (1997). A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy. ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 571–585. Pennington, NJ: Electrochemical Society.

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1997). A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 144(10), 3659–3664. https://doi.org/10.1149/1.1838066

Downey, D. F., Osburn, C. M., Cummings, J. J., Daryanani, S., & Falk, S. W. (1997, October 31). Dose-rate effects on the formation of ultra-shallow junctions with low-energy B+ and BF2+ ion implants. THIN SOLID FILMS, Vol. 308, pp. 562–569. https://doi.org/10.1016/S0040-6090(97)00494-X

Hulfachor, R. B., Kim, K. W., Littlejohn, M. A., & Osburn, C. M. (1997). Effects of silicon layer properties on device reliability for 0.1-μm SOI n-MOSFET design strategies. IEEE Transactions on Electron Devices, 44(5), 815–821. https://doi.org/10.1109/16.568044

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1997). Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology. ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 587–597. Pennington, NJ: Electrochemical Society.

Sun, J. J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., & Masnari, N. A. (1997). The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's. IEEE TRANSACTIONS ON ELECTRON DEVICES, 44(9), 1491–1498. https://doi.org/10.1109/16.622606

Zhang, K. X., & Osburn, C. M. (1997). The impact of in-situ rapid thermal gate dielectric processes on deep submicron MOSFETs. SOLID-STATE ELECTRONICS, 41(4), 619–625. https://doi.org/10.1016/S0038-1101(96)00195-5

Downey, D. F., Osburn, C. M., & Marcus, S. D. (1997). Ultrashallow junction formation by ion implant and RTA. Solid State Technology, 40(12), 71.

Sun, J., Bartholomew, R. F., Bellur, K., ONeil, P. A., Srivastava, A., Violette, K. E., … Masnari, N. A. (1996). Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition. RAPID THERMAL AND INTEGRATED PROCESSING V, Vol. 429, pp. 343–347. https://doi.org/10.1557/proc-429-343