Paul D. Franzon

A Deep Transfer Learning Design Rule Checker With Synthetic Training

IEEE DESIGN & TEST, 40(1), 77–84.

Chiplet Set For Artificial Intelligence

2023 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE, 3DIC.

Thermal Cycling and Fatigue Life Analysis of a Laterally Conducting GaN-based Power Package

2023 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2023 IEEE International 3D Systems Integration Conference (3DIC).

Thermal Estimation for 3D-ICs through Generative Networks

2023 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE, 3DIC.

Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 30(9), 1230–1243.

FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS

2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022), pp. 113–121.

Hardware Implementation of Hierarchical Temporal Memory Algorithm

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 18(1).

High Dimensional Optimization for Electronic Design

MLCAD '22: PROCEEDINGS OF THE 2022 ACM/IEEE 4TH WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD), pp. 153–157.

Modeling of Adaptive Receiver Performance Using Generative Adversarial Networks

IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022), pp. 1958–1963.

RxGAN: Modeling High-Speed Receiver through Generative Adversarial Networks

MLCAD '22: PROCEEDINGS OF THE 2022 ACM/IEEE 4TH WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD), pp. 167–172.

2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 40(6), 1217–1229.

A 125 mu m x 245 mu m Mainly Digital UHF EPC Gen2 Compatible RFID Tag in 55 nm CMOS Process

IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION, 5(3), 317–323.

A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation

2021 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC).

A Scalable Cluster-based Hierarchical Hardware Accelerator for a Cortically Inspired Algorithm

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 17(4).

Design Benefits of Hybrid Bonding for 3D Integration

IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), pp. 1876–1881.

Design for 3D Stacked Circuits

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM).

Fast and Accurate PPA Modeling with Transfer Learning

2021 ACM/IEEE 3RD WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD).

Fast and Accurate PPA Modeling with Transfer Learning

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). Presented at the 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Munich, Germany.

High Speed Receiver Modeling Using Generative Adversarial Networks

IEEE 30TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS 2021).

Multi-ANN embedded system based on a custom 3D-DRAM

2021 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC).

Application of Quantum Machine Learning to VLSI Placement

PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20), pp. 61–66.

Asymmetric Transformer Design With Multiband Frequency Response for Simultaneous Power and Data Transfer

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 10(4), 644–653.

CTLE Adaptation Using Deep Learning in High-speed SerDes Link

2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020), pp. 952–955.

Design Rule Checking with a CNN Based Feature Extractor

PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20), pp. 9–14.

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk

2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD).

Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 25(5).

Self-Evolution Cascade Deep Learning Model for High-Speed Receiver Adaptation

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 10(6), 1043–1053.

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 66(2), 756–768.

Appliance Identification Algorithm for a Non-Intrusive Home Energy Monitor Using Cogent Confabulation

IEEE Transactions on Smart Grid, 10(1), 714–721.

Handbook of 3D Integration: Design, Test, and Thermal Management

3D Design Styles

In P. Franzon, E. Martissen, & M. Bakir (Eds.), 3D Handbook Design and Test. Wiley.

3D Integration: Technology and Design

In K. Sakuma (Ed.), 3D Integration in VLSI Circuits.

3DIC Handbook Design and Test

Wiley.

Electronic Design Automaton for 3D

In P. Franzon, E. Martissen, & M. Bakir (Eds.), 3D Handbook Design and Test. Wiley.

Exploring the Tradeoffs of Application-Specific Processing

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 8(3), 531–542.

On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

JOURNAL OF ELECTRONIC MATERIALS, 47(2), 994–997.

Corrections to “Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding”[ Aug 13 1562-1567]

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(5), 1792–1792.

H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor

2017 IEEE International Conference on Computer Design (ICCD), 145–152.

A Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing RFICs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(3), 1151–1164.

Design and ASIC acceleration of cortical algorithm for text recognition

2016 29th IEEE International System-on-Chip Conference (SOCC). Presented at the 2016 29th IEEE International System-on-Chip Conference (SOCC).

Design of a rectifier-free UHF Gen-2 compatible RFID Tag using RF-only logic

2016 IEEE International Conference on RFID (RFID). Presented at the 2016 IEEE International Conference on RFID (RFID).

Hardware implementation of Hierarchical Temporal Memory algorithm

2016 29th IEEE International System-on-Chip Conference (SOCC). Presented at the 2016 29th IEEE International System-on-Chip Conference (SOCC).

Machine learning in physical design

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS). Presented at the 2016 IEEE 25th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).

Multimode High-Density Link Design Methodology and Implementation

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 6(8), 1251–1260.

Novel packaging and thermal measurement for 3D heterogeneous stacks

2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM). Presented at the 2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM), Raleigh, NC.

Physical design of a 3D-stacked heterogeneous multi-core processor

2016 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2016 IEEE International 3D Systems Integration Conference (3DIC), -San Francisco, CA.

Processor-in-memory support for artificial neural networks

2016 IEEE International Conference on Rebooting Computing (ICRC). Presented at the 2016 IEEE International Conference on Rebooting Computing (ICRC).

RDL and interposer design for DiRAM4 interfaces

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS). Presented at the 2016 IEEE 25th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).

Thermal raman and IR measurement of heterogeneous integration stacks

2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 1505–1510.

A Multitier Study on Various Stacking Topologies of TSV-Based PDN Systems Using On-Chip Decoupling Capacitor Models

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 5(4), 541–550.

Characterization of the Mechanical Stress Impact on Device Electrical Performance in the CMOS and III-V HEMT/HBT Heterogeneous Integration Environment

Proceedings Gomactech 2015.

Characterization of the mechanical stress impact on device electrical performance in the CMOS and III–V HEMT/HBT heterogeneous integration environment

2015 International 3D Systems Integration Conference (3DIC). Presented at the 2015 International 3D Systems Integration Conference (3DIC).

Chip Package Codesign

In L. Scheffer, L. Lavagno, & G. Martin (Eds.), The Handbook for EDA of Electronic Circuits (Second). CRC Press.

Computing in 3D

2015 IEEE Custom Integrated Circuits Conference (CICC). Presented at the 2015 IEEE Custom Integrated Circuits Conference - CICC 2015.

Computing in 3D

2015 International 3D Systems Integration Conference (3DIC). Presented at the 2015 International 3D Systems Integration Conference (3DIC), Sendai, Japan.

Defense Applications of 3DIC

Proceedings Gomactech 2015.

Optimization for Self-Calibrating Circuits

In Semiconductor Devices in Harsh Conditions. CRC.

Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks

2015 International 3D Systems Integration Conference (3DIC), 1–3.

3D-enabled customizable embedded computer (3DECC)

2014 International 3D Systems Integration Conference (3DIC). Presented at the 2014 International 3D Systems Integration Conference (3DIC).

A 0.65 mW/Gbps 30 Gbps capacitive coupled 10 mm serial link in 2.5D silicon interposer

2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems. Presented at the 2014 IEEE 23rd Electrical Performance of Electronic Packaging and Systems (EPEPS).

A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(12), 2701–2712.

Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4(11), 1862–1870.

Advances in TSVs and 3D interconnects

2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems. Presented at the 2014 IEEE 23rd Electrical Performance of Electronic Packaging and Systems (EPEPS).

Dual Floating Gate Unified Memory MOSFET With Simultaneous Dynamic and Non-Volatile Operation

IEEE ELECTRON DEVICE LETTERS, 35(1), 48–50.

Leveraging 3D-IC for on-chip timing uncertainty measurements

2014 International 3D Systems Integration Conference (3DIC). Presented at the 2014 International 3D Systems Integration Conference (3DIC).

Millimeter-Scale True 3-D Antenna-in-Package Structures for Near-Field Power Transfer

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4(10), 1574–1581.

Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC

2014 IEEE International Conference on IC Design & Technology. Presented at the 2014 IEEE International Conference on IC Design & Technology (ICICDT).

Storage Class Memories

In A. Chen, J. Hutchby, V. Zhrinov, & G. Bourianoff (Eds.), Emerging Nanoelectronic Devices. Wiley.

Thermal Pathfinding for 3-D ICs

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4(7), 1159–1168.

Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits

2014 International 3D Systems Integration Conference (3DIC). Presented at the 2014 International 3D Systems Integration Conference (3DIC).

A Bounded and Discretized Nelder-Mead Algorithm Suitable for RFIC Calibration

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 60(7), 1787–1799.

A compact inductively coupled connector for mobile devices

2013 IEEE 63rd Electronic Components and Technology Conference (ECTC), 2385–2390.

Applications and design styles for 3DIC

2013 IEEE International Electron Devices Meeting. Presented at the 2013 IEEE International Electron Devices Meeting (IEDM), Washington, DC.

Circuit/channel co-design methodology for multimode signaling

2013 IEEE 63rd Electronic Components and Technology Conference (ECTC), 1356–1361.

Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 21(8), 1562–1567.

Design and test of 2.5D and 3D stacked ICs

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems. Presented at the 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).

Design of 60 GHz contact less probe system for RDL in passive silicon interposer

2013 ieee international 3d systems integration conference (3dic).

Design of controller for L2 cache mapped in Tezzaron stacked DRAM

2013 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA.

Exploring early design tradeoffs in 3DIC

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 545–549.

Face-to-face bus design with built-in self-test in 3D ICS

2013 ieee international 3d systems integration conference (3dic).

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

Investigation of intermediate dielectric for dual floating gate MOSFET

2013 13th Non-Volatile Memory Technology Symposium (NVMTS).

MOOCs, OOCs, flips and hybrids: The new world of higher education

Proceedings ieee international conference on microelectronic systems, 13–13.

Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects

2013 IEEE 63rd Electronic Components and Technology Conference (ECTC), 860–866.

Rationale for a 3D heterogeneous multi-core processor

2013 IEEE 31st International Conference on Computer Design (ICCD), 154–168.

Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates

In VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design (pp. 217–233).

TSV-based, modular and collision detectable face-to-back shared bus design

2013 ieee international 3d systems integration conference (3dic).

Thermal requirements in future 3D processors

2013 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2013 IEEE International 3D Systems Integration Conference (3DIC).

Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models

SIMULATION AND MODELING METHODOLOGIES, TECHNOLOGIES AND APPLICATIONS, Vol. 197, pp. 255–269.

A 10.35 mW/GFlop Stacked SAR DSP unit using fine-grain partitioned 3D integration

2012 ieee custom integrated circuits conference (cicc).

A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits

IEEE Trans CPMT, P(99), 1.

A compact dielectric elastomer tubular actuator for refreshable Braille displays

SENSORS AND ACTUATORS A-PHYSICAL, 179, 151–157.

A novel double floating-gate unified memory device

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). Presented at the 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

An analysis of subthreshold SRAM bitcells for operation in low power RF-only technologies

2012 IEEE subthreshold microelectronics conference (SUBVT).

Analog Negative-Bias-Temperature-Instability Monitoring Circuit

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 12(1), 177–179.

Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 28(1), 27–38.

Comparison of TSV-based PDN-design effects using various stacking topology methods

Ieee conference on electrical performance of electronic packaging and, 83–86.

Comparison of modeling techniques in circuit variability analysis

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 25(3), 288–302.

Coordinating 3D designs: Interface IP, standards or free form?

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International. Presented at the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan.

Demystifying Surrogate Modeling for Circuits and Systems

IEEE Circuits and Systems Magazine, 12(1), 45–63.

Design, modeling, and fabrication of mm(3) three-dimensional integrated antennas

2012 IEEE 62nd Electronic Components and Technology Conference (ECTC), 1794–1799.

Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels

IET Circuits, Devices & Systems, 6(1), 35.

Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(5), 676–689.

Near threshold RF-only analog to digital converter

2012 IEEE subthreshold microelectronics conference (SUBVT).

Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 31(10), 1522–1535.

Pathfinder 3D: A flow for system-level design space exploration

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International. Presented at the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan.

Process mismatch analysis based on reduced-order models

2012 13th international symposium on quality electronic design (isqed), 648–655.

S-parameter based multimode signaling

Ieee conference on electrical performance of electronic packaging and, 11–14.

Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits

IEEE Design Test of Computers, 29(6), 74–83.

3D specific systems design and CAD

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Presented at the 2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XI).

3D specific systems: Design and CAD

2011 Asian Test Symposium, 470–473.

Accurate and Scalable IO Buffer Macromodel Based on Surrogate Modeling

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 1(8), 1240–1249.

Adaptive clock distribution for 3D integrated circuits

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 91–94.

Analysis and approach of TSV-based hierarchical power distribution networks for estimating 1st-droop and resonant noise in 3DIC

Ieee conference on electrical performance of electronic packaging and, 267–270.

Computing with Novel Floating-Gate Devices

COMPUTER, 44(2), 29–36.

Design strategies for processor, chip/package co-design (M-VI)

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems. Presented at the 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).

Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor

IET COMPUTERS AND DIGITAL TECHNIQUES, 5(3), 198–204.

SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation

IET CIRCUITS DEVICES & SYSTEMS, 5(6), 477–483.

Surrogate Model-Based Analysis of Analog Circuits – Part I. Variability Analysis

IEEE Transactions on Device and Materials Reliability, PP(99).

A zero power consumption Multi-Capacitor structure for voltage summing in high-speed FFE

19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems. Presented at the 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).