@article{francisco_davis_franzon_2023, title={A Deep Transfer Learning Design Rule Checker With Synthetic Training}, volume={40}, ISSN={["2168-2364"]}, url={https://doi.org/10.1109/MDAT.2022.3162786}, DOI={10.1109/MDAT.2022.3162786}, abstractNote={Deep transfer learning is applied to the task of design rule checking (DRC). A parameterized synthetic data set generator is used to train the model. —Ulf Schlichtmann, Technical University of Munich}, number={1}, journal={IEEE DESIGN & TEST}, author={Francisco, Luis and Davis, W. Rhett and Franzon, Paul}, year={2023}, month={Feb}, pages={77–84} }
 @article{stevens_pan_ravichandiran_franzon_2023, title={Chiplet Set For Artificial Intelligence}, ISSN={["2164-0157"]}, DOI={10.1109/3DIC57175.2023.10154953}, abstractNote={The design reuse strategy has significantly shortened the time required to create complex System on Chips (SoCs). However, when introducing new intellectual properties (IPs), the monolithic SoC methodology requires a re-run of system-level validation steps, incurring significant costs. Partitioning the design into chiplets over an interposer would mitigate these issues by consigning the IP updates to the individual chiplet. This paper presents a chipletized design used for Artificial Intelligence (AI). This design details a scalable AI chiplet set, along with Central Processing Units (CPUs). The AI chiplet set includes an Long Short Term Memory (LSTM) Application Specific Instruction Set Processor (ASIP) for accelerating inference and training and an Sparse Convolution Neural Network (SCNN) ASIP for accelerating inference through a zero-skipping technique. The CPUs control AI accelerators and handle general tasks. The accelerators and CPUs have an AXI crossbar Network on Chip (NoC) for memory and one for controlling the accelerators. This project has two phases: phase one, IP validation with an emulated interposer (No interposer, connect chiplets through back end of line (BEOL) metal layers), and phase two, connecting validated IP through an interposer. This paper focuses on phase one, which uses the United Semiconductor Japan Co. (USJC) 55 nm LP process to fabricate the design. The chiplets' clock frequencies range from 200 - 400 MHz.}, journal={2023 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE, 3DIC}, author={Stevens, Joshua A. and Pan, Tse-Han and Ravichandiran, Prasanth Prabu and Franzon, Paul D.}, year={2023} }
 @article{kashyap_cheng_choi_franzon_2023, title={Generative Multi-Physics Models for System Power and Thermal Analysis Using Conditional Generative Adversarial Networks}, ISSN={["2165-4107"]}, DOI={10.1109/EPEPS58208.2023.10314864}, abstractNote={As system performance increases, chip density and power consumption also increase. Power integrity and thermal management have become critical to the design flow and are codependent on each other. Advanced simulation tools perform co-simulation of electrical and thermal analysis on package-board designs. This paper describes a novel way of using a class of deep learning algorithms called conditional GANs (cGANs) to efficiently model the power/thermal co-simulation task. As the name suggests, cGANs are generative models that can predict unseen simulation conditions. Using the cGAN, the root-mean-squared error on unseen test cases is 0.015 in a [-1,1] range, translating to an error under 0.3 C°. Furthermore, a trained network exhibits fast inference speeds, allowing for near real-time generation of analysis results. This is a common goal of digital twins for dynamic system performance tuning.}, journal={2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS}, author={Kashyap, Priyank and Cheng, Chris and Choi, Yongjin and Franzon, Paul}, year={2023} }
 @article{pan_franzon_srinivas_nagarajan_popovic_2023, title={System Aware Floorplanning for Chip-Package Co-design}, ISSN={["2165-4107"]}, DOI={10.1109/EPEPS58208.2023.10314897}, abstractNote={SoC floorplanning is crucial as it bridges the system design and the physical design of the chip. In this paper, we present a new floorplanning solution based on a novel floorplan model that more closely depicts the design challenges imposed by modern SoC system constraints. Our experimental results demonstrated that this solution is able to create floorplans with hard peripheral instances and soft rectilinear instances with zero white space while supporting system constraints on multiple design instances.}, journal={2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS}, author={Pan, Tse-Han and Franzon, Paul D. and Srinivas, Vaishnav and Nagarajan, Mahalingam and Popovic, Darko}, year={2023} }
 @inproceedings{zaghari_sinha_ryu_franzon_hopkins_2023, title={Thermal Cycling and Fatigue Life Analysis of a Laterally Conducting GaN-based Power Package}, ISSN={["2164-0157"]}, url={http://dx.doi.org/10.1109/3dic57175.2023.10154901}, DOI={10.1109/3DIC57175.2023.10154901}, abstractNote={Thermal reliability is a critical factor in ensuring the performance and efficiency of GaN-based electronic devices. In this paper, the fatigue life assessment of a laterally conducting GaN power package that uses a two-solder hierarchy of SAC305 and Sn63/Pb37 on a 120μm thick dielectric for device attach was conducted using an FEA. The double-sided package structure also introduced thick Cu as integrated baseplate layers for mechanical mounting into higher packaging levels while providing surfaces for double-sided cooling. The internal structure varied spacer thicknesses for planarization and inclusion of package-integrated decoupling capacitors. The solder materials were simulated by using the Anand viscoplastic constitutive model. Coffin-Manson, Engelmaier, and Solomon empirical strain-based models were utilized to predict the cyclic life of the package. Based on the results, the critical solder joint location was predicted in the Sn63/Pb37 solder layer between the GaN and Cu spacer, with a strain range of 0.02797. The worst-case life prediction for the module was 150 cycles using the Coffin-Manson model.}, booktitle={2023 IEEE International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Zaghari, Pouria and Sinha, Sourish S. and Ryu, Jong Eun and Franzon, Paul D. and Hopkins, Douglas C.}, year={2023}, month={May} }
 @article{kashyap_ravichandiran_wang_baron_wong_wu_franzon_2023, title={Thermal Estimation for 3D-ICs through Generative Networks}, ISSN={["2164-0157"]}, DOI={10.1109/3DIC57175.2023.10154977}, abstractNote={Thermal limitations play a significant role in modern integrated chips (ICs) design and performance. 3D integrated chip (3DIC) makes the thermal problem even worse due to a high density of transistors and heat dissipation bottlenecks within the stack-up. These issues exacerbate the need for quick thermal solutions throughout the design flow. This paper presents a generative approach for modeling the power to heat dissipation for a 3DIC. This approach focuses on a single layer in a stack and shows that, given the power map, the model can generate the resultant heat for the bulk. It shows two approaches, one straightforward approach where the model only uses the power map and the other where it learns the additional parameters through random vectors. The first approach recovers the temperature maps with 1.2 C° or a root-mean-squared error (RMSE) of 0.31 over the images with pixel values ranging from -1 to 1. The second approach performs better, with the RMSE decreasing to 0.082 in a 0 to 1 range. For any result, the model inference takes less than 100 millisecond for any given power map. These results show that the generative approach has speed advantages over traditional solvers while enabling results with reasonable accuracy for 3DIC, opening the door for thermally aware floorplanning.}, journal={2023 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE, 3DIC}, author={Kashyap, Priyank and Ravichandiran, Prasanth P. and Wang, Lee and Baron, Dror and Wong, Chau-Wai and Wu, Tianfu and Franzon, Paul D.}, year={2023} }
 @article{nigussie_schabel_lipa_mcilrath_patti_franzon_2022, title={Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning}, volume={30}, ISSN={["1557-9999"]}, url={https://doi.org/10.1109/TVLSI.2022.3179304}, DOI={10.1109/TVLSI.2022.3179304}, abstractNote={We describe a design and fabrication experiment that has been performed to investigate a methodology for assessing the security of application specific integrated circuits (ASICs) fabricated in a split-manufacturing process based on 3-D integrated circuit (3DIC) technologies. The purpose of this process is to protect critical IP from reverse engineering if an adversary obtains either the fabricated wafers or their GDS. A number of 3DIC-based fabrication alternatives were evaluated, and one is selected for this experiment. Several designs, from the trivial to the complex, were used for the study. A self-test module was embedded in each design to facilitate the postfabrication testing. Various obfuscation techniques that include camouflage in the form of function and lookup table hiding and insertion of redundant logic in order to confuse potential attackers were applied. Smart partitioning was implemented for each design in an attempt to conceal vital functions. We introduced metrics that are based on the number of connection possibilities (<inline-formula> <tex-math notation="LaTeX">$C_{p}$ </tex-math></inline-formula>) and the depth of partitioning (<inline-formula> <tex-math notation="LaTeX">$P_{\mathrm{ depth}}$ </tex-math></inline-formula>) to measure the obfuscation strength. The results show that it should take more than 10 <sup>60</sup> years to reconstruct the netlist using a brute-force attack. Measurement results are presented showing fabrication success.}, number={9}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Nigussie, Theodros and Schabel, Josh C. and Lipa, Steve and McIlrath, Lisa and Patti, Robert and Franzon, Paul}, year={2022}, month={Sep}, pages={1230–1243} }
 @article{gajjar_kashyap_aysu_franzon_dey_cheng_2022, title={FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS}, ISSN={["2576-2621"]}, url={http://dx.doi.org/10.1109/fccm53951.2022.9786085}, DOI={10.1109/FCCM53951.2022.9786085}, abstractNote={Advanced ensemble trees have proven quite effective in providing real-time predictions against ransomware detection, medical diagnosis, recommendation engines, fraud detection, failure predictions, crime risk, to name a few. Especially, XGBoost, one of the most prominent and widely used decision trees, has gained popularity due to various optimizations on gradient boosting framework that provides increased accuracy for classification and regression problems. XGBoost’s ability to train relatively faster, handling missing values, flexibility and parallel processing make it a better candidate to handle data center workload. Today’s data centers with enormous Input/Output Operations per Second (IOPS) demand a real-time accelerated inference with low latency and high throughput because of significant data processing due to applications such as ransomware detection or fraud detection.This paper showcases an FPGA-based XGBoost accelerator designed with High-Level Synthesis (HLS) tools and design flow accelerating binary classification inference. We employ Alveo U50 and U200 to demonstrate the performance of the proposed design and compare it with existing state-of-the-art CPU (Intel Xeon E5-2686 v4) and GPU (Nvidia Tensor Core T4) implementations with relevant datasets. We show a latency speedup of our proposed design over state-of-art CPU and GPU implementations, including energy efficiency and cost-effectiveness. The proposed accelerator is up to 65.8x and 5.3x faster, in terms of latency than CPU and GPU, respectively. The Alveo U50 is a more cost-effective device, and the Alveo U200 stands out as more energy-efficient.}, journal={2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022)}, publisher={IEEE}, author={Gajjar, Archit and Kashyap, Priyank and Aysu, Aydin and Franzon, Paul and Dey, Sumon and Cheng, Chris}, year={2022}, pages={113–121} }
 @article{li_franzon_dey_schabel_2022, title={Hardware Implementation of Hierarchical Temporal Memory Algorithm}, volume={18}, ISSN={["1550-4840"]}, DOI={10.1145/3479430}, abstractNote={
            Hierarchical temporal memory (HTM)
            is an un-supervised machine learning algorithm that can learn both spatial and temporal information of input. It has been successfully applied to multiple areas. In this paper, we propose a multi-level hierarchical ASIC implementation of HTM, referred to as processor core, to support both spatial and temporal pooling. To improve the unbalanced workload in HTM, the proposed design provides different mapping methods for the spatial and temporal pooling, respectively. In the proposed design, we implement a distributed memory system by assigning one dedicated memory bank to each level of hierarchy to improve the memory bandwidth utilization efficiency. Finally, the hot-spot operations are optimized using a series of customized units. Regarding scalability, we propose a ring-based network consisting of multiple processor cores to support a larger HTM network. To evaluate the performance of our proposed design, we map an HTM network that includes 2,048 columns and 65,536 cells on both the proposed design and NVIDIA Tesla K40c GPU using the KTH database as input. The latency and power of the proposed design is 6.04 ms and 4.1 W using GP 65 nm technology. Compared to the equivalent GPU implementation, the latency and power is improved 12.45× and 57.32×, respectively.
          }, number={1}, journal={ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS}, author={Li, Weifu and Franzon, Paul and Dey, Sumon and Schabel, Joshua}, year={2022}, month={Jan} }
 @article{wen_dean_floyd_franzon_2022, title={High Dimensional Optimization for Electronic Design}, DOI={10.1145/3551901.3556495}, abstractNote={Bayesian optimization (BO) samples points of interest to update a surrogate model for a blackbox function. This makes it a powerful technique to optimize electronic designs which have unknown objective functions and demand high computational cost of simulation. Unfortunately, Bayesian optimization suffers from scalability issues, e.g., it can perform well in problems up to 20 dimensions. This paper addresses the curse of dimensionality and proposes an algorithm entitled Inspection-based Combo Random Embedding Bayesian Optimization (IC-REMBO). IC-REMBO improves the effectiveness and efficiency of the Random EMbedding Bayesian Optimization (REMBO) approach, which is a state-of-the-art high dimensional optimization method. Generally, it inspects the space near local optima to explore more points near local optima, so that it mitigates the over-exploration on boundaries and embedding distortion in REMBO. Consequently, it helps escape from local optima and provides a family of feasible solutions when inspecting near global optimum within a limited number of iterations.The effectiveness and efficiency of the proposed algorithm are compared with the state-of-the-art REMBO when optimizing a mmWave receiver with 38 calibration parameters to meet 4 objectives. The optimization results are close to that of a human expert. To the best of our knowledge, this is the first time applying REMBO or inspection method to electronic design.}, journal={MLCAD '22: PROCEEDINGS OF THE 2022 ACM/IEEE 4TH WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD)}, author={Wen, Yuejiang and Dean, Jacob and Floyd, Brian A. and Franzon, Paul D.}, year={2022}, pages={153–157} }
 @article{kashyap_choi_dey_baron_wong_wu_cheng_franzon_2022, title={Modeling of Adaptive Receiver Performance Using Generative Adversarial Networks}, ISSN={["2377-5726"]}, url={http://dx.doi.org/10.1109/ectc51906.2022.00307}, DOI={10.1109/ECTC51906.2022.00307}, abstractNote={As the development of IBIS Algorithmic Modeling Interface (IBIS-AMI) models gets complex and requires time-consuming simulations, a data-driven and domain-independent approach can have tremendous value. This paper presents a data-driven approach to modeling a high-speed serializer/deserializer (SerDes) receiver through generative adversarial networks (GANs). In this work, the modeling considers multiple channels, random bitstreams, and varying decision feedback equalizer (DFE) tap values to predict an accurate bit error rate (BER) contour plot. We employ a discriminator structure that improves the training to generate a contour plot that makes it difficult to distinguish the ground truth. The generated plots’ bathtub curves strongly correlate to the ground truth bathtub curves and have a root-mean-squared error (RMSE) of 0.014, indicating a good fit.}, journal={IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022)}, publisher={IEEE}, author={Kashyap, Priyank and Choi, Yongjin and Dey, Sumon and Baron, Dror and Wong, Chau-Wai and Wu, Tianfu and Cheng, Chris and Franzon, Paul D.}, year={2022}, pages={1958–1963} }
 @article{kashyap_gajjar_choi_wong_baron_wu_cheng_franzon_2022, title={RxGAN: Modeling High-Speed Receiver through Generative Adversarial Networks}, url={http://dx.doi.org/10.1145/3551901.3556480}, DOI={10.1145/3551901.3556480}, abstractNote={Creating models for modern high-speed receivers using circuit-level simulations is costly, as it requires computationally expensive simulations and upwards of months to finalize a model. Added to this is that many models do not necessarily agree with the final hardware they are supposed to emulate. Further, these models are complex due to the presence of various filters, such as a decision feedback equalizer (DFE) and continuous-time linear equalizer (CTLE), which enable the correct operation of the receiver. Other data-driven approaches tackle receiver modeling through multiple models to account for as many configurations as possible. This work proposes a data-driven approach using generative adversarial training to model a real-world receiver with varying DFE and CTLE configurations while handling different channel conditions and bitstreams. The approach is highly accurate as the eye height and width are within 1.59% and 1.12% of the ground truth. The horizontal and vertical bathtub curves match the ground truth and correlate to the ground truth bathtub curves.}, journal={MLCAD '22: PROCEEDINGS OF THE 2022 ACM/IEEE 4TH WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD)}, publisher={ACM}, author={Kashyap, Priyank and Gajjar, Archit and Choi, Yongjin and Wong, Chau-Wai and Baron, Dror and Wu, Tianfu and Cheng, Chris and Franzon, Paul}, year={2022}, pages={167–172} }
 @article{kashyap_aydin_potluri_franzon_aysu_2021, title={2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning}, volume={40}, ISSN={["1937-4151"]}, url={http://dx.doi.org/10.1109/tcad.2020.3038701}, DOI={10.1109/TCAD.2020.3038701}, abstractNote={Advancements in quantum computing present a security threat to classical cryptography algorithms. Lattice-based key exchange protocols show strong promise due to their resistance to theoretical quantum-cryptanalysis and low implementation overhead. By contrast, their physical implementations have shown vulnerability against side-channel attacks (SCAs) even with a single power measurement. The state-of-the-art SCAs are, however, limited to simple, sequentialized executions of post-quantum key-exchange (PQKE) protocols, leaving the vulnerability of complex, parallelized architectures unknown. This article proposes 2Deep—a deep-learning (DL)-based SCA—targeting parallelized implementations of PQKE protocols, namely, <monospace>Frodo</monospace> and <monospace>NewHope</monospace> with data augmentation techniques. Specifically, we explore approaches that convert 1-D time-series power measurement data into 2-D images to formulate SCA an image recognition task. The results show our attack’s superiority over conventional techniques including horizontal differential power analysis (DPA), template attacks (TAs), and straightforward DL approaches. We demonstrate improvements up to <inline-formula> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> to recover a 100% success rate compared to DL with 1-D input data while using fewer data. We furthermore show that machine learning improves the results up to <inline-formula> <tex-math notation="LaTeX">$1.25\times $ </tex-math></inline-formula> compared to TAs. Furthermore, we perform cross-device attacks that obtain profiles from a single device, which has never been explored. Our 2-D approach is especially favored in this setting, improving the success rate of attacking <monospace>Frodo</monospace> from 20% to 99% compared to the 1-D approach. Our work thus urges countermeasures even on parallel architectures and single-trace attacks.}, number={6}, journal={IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Kashyap, Priyank and Aydin, Furkan and Potluri, Seetal and Franzon, Paul D. and Aysu, Aydin}, year={2021}, month={Jun}, pages={1217–1229} }
 @article{bhanushali_zhao_pitts_franzon_2021, title={A 125 mu m x 245 mu m Mainly Digital UHF EPC Gen2 Compatible RFID Tag in 55 nm CMOS Process}, volume={5}, ISSN={["2469-7281"]}, DOI={10.1109/JRFID.2021.3087448}, abstractNote={This paper presents a compact and largely digital UHF EPC Gen2-compatible RFID implemented using digital IP blocks that are easily portable. This is the first demonstration of a digital Gen2-compatible RFID tag chip with an area of $125{\mu }\text{m} \times 245{\mu }\text{m}$ and −2 dBm sensitivity operating in the 860–960MHz band. It is enabled by a) largely standard cell-based digital implementation using dual-phase RF-only logic approach, b) near-threshold voltage operation, and c) elimination of area intensive, complex, and less scalable rectifiers, storage capacitors, and power management units used in conventional RFID tags. In this demonstration, all but six cells were directly used from the standard cell library provided by the foundry. This makes it suitable for cost-sensitive applications, and as embedded RFIDs for tagging counterfeit Integrated Circuits (ICs).}, number={3}, journal={IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION}, author={Bhanushali, Kirti and Zhao, Wenxu and Pitts, W. Shepherd and Franzon, Paul D.}, year={2021}, month={Sep}, pages={317–323} }
 @article{ravichandiran_franzon_2021, title={A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation}, ISSN={["2164-0157"]}, DOI={10.1109/3DIC52383.2021.9687615}, abstractNote={The growth of Neural Networks (NNs) and Machine Learning (ML) usage has rapidly increased over the last decade. Traditional dynamic random-access memory (DRAM) is struggling to meet the computational, throughput demands of these NNs and has become a bottleneck in the system. One of the commonly proposed solutions is Near-Memory Computation (NMC) hardware accelerators to move the computation closer to the data resulting in improved throughput and reduced power consumption. In this paper, we analyze a few critical NMC architecture implementations, specifically those with 3D-Stacked DRAM memory. We have organized a literature review across structures, configuration, application, performance metrics, and present challenges and opportunities.}, journal={2021 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC)}, author={Ravichandiran, Prasanth Prabu and Franzon, Paul D.}, year={2021} }
 @article{dey_baker_schabel_li_franzon_2021, title={A Scalable Cluster-based Hierarchical Hardware Accelerator for a Cortically Inspired Algorithm}, volume={17}, ISSN={["1550-4840"]}, DOI={10.1145/3447777}, abstractNote={This article describes a scalable, configurable and cluster-based hierarchical hardware accelerator through custom hardware architecture for Sparsey, a cortical learning algorithm. Sparsey is inspired by the operation of the human cortex and uses a Sparse Distributed Representation to enable unsupervised learning and inference in the same algorithm. A distributed on-chip memory organization is designed and implemented in custom hardware to improve memory bandwidth and accelerate the memory read/write operations for synaptic weight matrices. Bit-level data are processed from distributed on-chip memory and custom multiply-accumulate hardware is implemented for binary and fixed-point multiply-accumulation operations. The fixed-point arithmetic and fixed-point storage are also adapted in this implementation. At 16 nm, the custom hardware of Sparsey achieved an overall 24.39×  speedup, 353.12× energy efficiency per frame, and 1.43× reduction in silicon area against a state-of-the-art GPU.}, number={4}, journal={ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS}, author={Dey, Sumon and Baker, Lee and Schabel, Joshua and Li, Weifu and Franzon, Paul D.}, year={2021}, month={Oct} }
 @article{nigussie_pan_lipa_pitts_delacruz_franzon_2021, title={Design Benefits of Hybrid Bonding for 3D Integration}, ISSN={["2377-5726"]}, DOI={10.1109/ECTC32696.2021.00296}, abstractNote={We present electrical and thermal analyses of 3D digital designs using hybrid bonding, specifically using the design rules, and other properties, for the XPERI DBI® technology at a $\mathrm{1.6}\ \mu \mathrm{m}$ pad pitch. We also go over the advantages of hybrid bonding over thermo-compression bonding (TCB) and 2D designs. Commercial 3D physical design tools were not mature when we did this work, so we came up with a methodology that builds on 2D tools. Our design flow includes scripts for optimal assignment of bonding locations, partitioning of netlist and delay constraints, and optimization techniques that involve iterating on delay constraints. Various partitioning schemes that include targeting long nets, managing flip-flop distribution between tiers, and minimum cut partitioning using an open source tool were analyzed. Because analysis results could vary from design to design, we propose potential metrics that can be used to identify designs that may benefit from 3DIC technology. Analysis results showed that we were able to reduce routed wire length by up to 57%. Logic power and total power decreased by up to 34% and 22% respectively. Silicon area also improved by 11%.11This work was supported, in part, by Xperi. DISTRIBUTION STATE-MENT A. Approved for public release: distribution unlimited.}, journal={IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021)}, author={Nigussie, Theodros and Pan, Tse-Han and Lipa, Steve and Pitts, W. Shepherd and DeLaCruz, Javi and Franzon, Paul}, year={2021}, pages={1876–1881} }
 @article{franzon_davis_rotenberg_stevens_lipa_nigussie_pan_baker_schabel_dey_et al._2021, title={Design for 3D Stacked Circuits}, ISSN={["2380-9248"]}, DOI={10.1109/IEDM19574.2021.9720553}, abstractNote={2.5D and 3D technologies can give rise to a node equivalent of scaling due to improved connectivity. Aggressive exploitation scenarios include functional partitioning, circuit partitioning, logic on DRAM, design obfuscation and modular chiplets. Design issues that need to be addressed in pursuing such exploitations include thermal management, design for test and computer aided design.}, journal={2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)}, author={Franzon, P. and Davis, W. and Rotenberg, E. and Stevens, J. and Lipa, S. and Nigussie, T. and Pan, H. and Baker, L. and Schabel, J. and Dey, S. and et al.}, year={2021} }
 @article{francisco_franzon_davis_2021, title={Fast and Accurate PPA Modeling with Transfer Learning}, DOI={10.1109/MLCAD52597.2021.9531109}, abstractNote={The power, performance, and area (PPA) of a System-on-Chip (SoC) is known only after a months-long process. This process includes iterations over the architectural design, register transfer level implementation, RTL synthesis, and place and route. Knowing the PPA estimates for a system early in the design stages can help resolve tradeoffs that will affect the final design. This work presents a machine learning approach using gradient boost models and neural networks to fast and accurately predict the PPA. This work focuses on reducing the number of samples used to create the models. The models use transfer learning to predict the PPA for new design configurations and corner conditions based on previous models. The models predict the PPA as a function of parameters accessible during the RTL synthesis. The proposed models achieved PPA predictions up to 99% accurate and using as few as 10 data samples can achieve accuracies better than 96%.}, journal={2021 ACM/IEEE 3RD WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD)}, author={Francisco, Luis and Franzon, Paul and Davis, W. Rhett}, year={2021} }
 @inproceedings{davis_franzon_francisco_huggins_jain_2021, title={Fast and Accurate PPA Modeling with Transfer Learning}, ISSN={["1933-7760"]}, DOI={10.1109/ICCAD51958.2021.9643533}, abstractNote={The power, performance and area (PPA) of digital blocks can vary 10:1 based on their synthesis, place, and route tool recipes. With rapid increase in number of PVT corners and complexity of logic functions approaching 10M gates, industry has an acute need to minimize the human resources, compute servers, and EDA licenses needed to achieve a Pareto optimal recipe. We first present models for fast accurate PPA prediction that can reduce the manual optimization iterations with EDA tools. Secondly we investigate techniques to automate the PPA optimization using evolutionary algorithms. For PPA prediction, a baseline model is trained on a known design using Latin hypercube sample runs of the EDA tool, and transfer learning is then used to train the model for an unseen design. For a known design the baseline needed 150 training runs to achieve a 95% accuracy. With transfer learning the same accuracy was achieved on a different (unseen) design in only 15 runs indicating the viability of transfer learning to generalize PPA models. The PPA optimization technique, based on evolutionary algorithms, effectively combines the PPA modeling and optimization. Our approach reached the same PPA solution as human designers in the same or fewer runs for a CORTEX-M0 system design. This shows potential for automating the recipe optimization without needing more runs than a human designer would need.}, booktitle={2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)}, author={Davis, W.R. and Franzon, P. and Francisco, L. and Huggins, B. and Jain, R.}, year={2021} }
 @article{kashyap_pitts_baron_wong_wu_franzon_2021, title={High Speed Receiver Modeling Using Generative Adversarial Networks}, ISSN={["2165-4107"]}, DOI={10.1109/EPEPS51341.2021.9609124}, abstractNote={This paper presents a generative approach to modeling a high-speed receiver with a time series input. The model is not built with domain knowledge but learned from a wide range of channel conditions and input bitstreams to generate an eye diagram. The generated eye diagrams are similar to the simulated eye diagrams for the same scenario. We also developed a neural network model to evaluate the generated eye diagram's relevant characteristics, such as eye height and width. The generated eye diagrams are within 7% and 3% error to the ground-truth in eye height and eye width, respectively, based on our evaluation neural network.}, journal={IEEE 30TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS 2021)}, author={Kashyap, Priyank and Pitts, W. Shepherd and Baron, Dror and Wong, Chau-Wai and Wu, Tianfu and Franzon, Paul D.}, year={2021} }
 @article{baker_patti_franzon_2021, title={Multi-ANN embedded system based on a custom 3D-DRAM}, ISSN={["2164-0157"]}, DOI={10.1109/3DIC52383.2021.9687617}, abstractNote={Machine Learning in the form of Artificial Neural Networks (ANNs) has gained considerable traction in applications such as image recognition and speech recognition. These applications typically employ a subset of ANNs known as Convolutional Neural Networks (CNNs) which re-use parameters and thus reduce main memory bandwidth. However, there are other types of ANN that do not provide reuse opportunities such as autoencoders and Long Short-term memory. Most research has focused on implementing CNNs but because of their extensive use of SRAM have both ANN size restrictions and performance degradation when used in applications that utilize other types of ANN. This work demon-strates how a customized 3D-DRAM with a very wide databus can be combined with application-specific layers to produce a system meeting the requirements of embedded systems employing multiple instances of disparate ANNs.}, journal={2021 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC)}, author={Baker, Lee B. and Patti, Robert and Franzon, Paul}, year={2021} }
 @article{turtletaub_li_ibrahim_franzon_2020, title={Application of Quantum Machine Learning to VLSI Placement}, DOI={10.1145/3380446.3430644}, abstractNote={Considerable advances in quantum computing with functioning noisy, near-term devices have allowed for the application space to grow as a emerging field for problems with large solution spaces. However, current quantum hardware is limited in scale and noisy in generated data, necessitating hybrid quantum-classical solutions for viability of results and convergence. A quantum backend generates data for classical algorithms to optimize control parameters with, creating a hybrid quantum-classical computing loop. VLSI placement problems have shown potential for utilization, where traditionally heuristic solutions such as Kernighan-Lin (KL) are used. The Variational Quantum Eigensolver (VQE) is used to formulate a recursive Balanced Min-Cut (BMC) algorithm, and we suggest that quantum machine learning techniques can lower error rates and allow for faster convergence to an optimal solution.}, journal={PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20)}, author={Turtletaub, Isaac and Li, George and Ibrahim, Mohannad and Franzon, Paul}, year={2020}, pages={61–66} }
 @article{zannat_franzon_2020, title={Asymmetric Transformer Design With Multiband Frequency Response for Simultaneous Power and Data Transfer}, volume={10}, ISSN={["2156-3985"]}, DOI={10.1109/TCPMT.2020.2977045}, abstractNote={This article presents a novel approach to generate multiple passbands from an asymmetric two-coil transformer. The details of the asymmetry between the primary and secondary coils control the passbands’ location and bandwidth (BW). A cylindrical asymmetric connector was designed and prototyped. The S-parameters were measured with a vector network analyzer (VNA), which shows a very good match with the theoretical model up to the second passband frequency (10 MHz–1 GHz). The first passband is used for power transfer since the lower frequency is better for power transmission. The higher frequency of the second passband can be used to transmit high BW data. A carrier signal centered at the second passband frequency was used to modulate digital data at the transmitter side and demodulated at the receiver side. This connector can be used for transmitting only power, or only data, or both power and data simultaneously. We demonstrate 19 mW of power transfer and 100 Mb/s of data transfer simultaneously in a 5-mm-diameter and 7-mm high cylindrically coupled structure. To the best of our knowledge, it is the highest data rate demonstrated through a wireless power transfer link.}, number={4}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Zannat, Nazia and Franzon, Paul D.}, year={2020}, month={Apr}, pages={644–653} }
 @article{li_jiao_chou_mayder_franzon_2020, title={CTLE Adaptation Using Deep Learning in High-speed SerDes Link}, ISSN={["2377-5726"]}, DOI={10.1109/ECTC32862.2020.00155}, abstractNote={To speed up a serial link simulation, it is critical to model the Serializer/Deserializer (SerDes) circuit behavior accurately. In this research, we focus on building a model for high-speed SerDes receiver CTLE adaptation behavior, which has a fast simulation speed and high-precision prediction. The proposed modeling method doesn’t need any substantial domain knowledge. Deep neural networks model will be used to mimic the behavior of the CTLE adaptation process in the receiver. The proposed modeling method shows high correlations with the CTLE adaptation codes.}, journal={2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020)}, author={Li, Bowen and Jiao, Brandon and Chou, Chih-Hsun and Mayder, Romi and Franzon, Paul}, year={2020}, pages={952–955} }
 @article{francisco_lagare_jain_chaudhary_kulkarni_sardana_davis_franzon_2020, title={Design Rule Checking with a CNN Based Feature Extractor}, DOI={10.1145/3380446.3430625}, abstractNote={Design rule checking (DRC) is getting increasingly complex in advanced nodes technologies. It would be highly desirable to have a fast interactive DRC engine that could be used during layout. In this work, we establish the proof of feasibility for such an engine. The proposed model consists of a convolutional neural network (CNN) trained to detect DRC violations. The model was trained with artificial data that was derived from a set of 50 SRAM designs. The focus in this demonstration was metal 1 rules. Using this solution, we can detect multiple DRC violations 32x faster than Boolean checkers with an accuracy of up to 92%. The proposed solution can be easily expanded to a complete rule set.}, journal={PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20)}, author={Francisco, Luis and Lagare, Tanmay and Jain, Arpit and Chaudhary, Somal and Kulkarni, Madhura and Sardana, Divya and Davis, W. Rhett and Franzon, Paul}, year={2020}, pages={9–14} }
 @article{regazzoni_bhasin_pour_alshaer_aydin_aysu_beroulle_di natale_franzon_hely_et al._2020, title={Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk}, ISSN={["1933-7760"]}, DOI={10.1145/3400302.3416260}, abstractNote={Machine learning techniques have significantly changed our lives. They helped improving our everyday routines, but they also demonstrated to be an extremely helpful tool for more advanced and complex applications. However, the implications of hardware security problems under a massive diffusion of machine learning techniques are still to be completely understood. This paper first highlights novel applications of machine learning for hardware security, such as evaluation of post quantum cryptography hardware and extraction of physically unclonable functions from neural networks. Later, practical model extraction attack based on electromagnetic side-channel measurements are demonstrated followed by a discussion of strategies to protect proprietary models by watermarking them.}, journal={2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD)}, author={Regazzoni, Francesco and Bhasin, Shivam and Pour, Amir Ali and Alshaer, Ihab and Aydin, Furkan and Aysu, Aydin and Beroulle, Vincent and Di Natale, Giorgio and Franzon, Paul and Hely, David and et al.}, year={2020} }
 @article{wang_franzon_smart_swahn_2020, title={Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration}, volume={25}, ISSN={["1557-7309"]}, DOI={10.1145/3398268}, abstractNote={As circuits’ speed and frequency increase, fast and accurate capture of the details of the parasitics in metal structures, such as inductors and clock trees, becomes more critical. However, conducting high-fidelity 3D electromagnetic (EM) simulations within the design loop is very time consuming and computationally expensive. To address this issue, we propose a surrogate-based optimization methodology flow, namely multi-fidelity surrogate-based optimization with candidate search (MFSBO-CS), which integrates the concept of multi-fidelity to reduce the full-wave EM simulation cost in analog/RF simulation-based optimization problems. To do so, a statistical co-kriging model is adapted as the surrogate to model the response surface, and a parallelizable perturbation-based adaptive sampling method is used to find the optima. Within the proposed method, low-fidelity fast RC parasitic extraction tools and high-fidelity full-wave EM solvers are used together to model the target design and then guide the proposed adaptive sample method to achieve the final optimal design parameters. The sampling method in this work not only delivers additional coverage of design space but also helps increase the accuracy of the surrogate model efficiently by updating multiple samples within one iteration. Moreover, a novel modeling technique is developed to further improve the multi-fidelity surrogate model at an acceptable additional computation cost. The effectiveness of the proposed technique is validated by mathematical proofs and numerical test function demonstration. In this article, MFSBO-CS has been applied to two design cases, and the result shows that the proposed methodology offers a cost-efficient solution for analog/RF design problems involving EM simulation. For the two design cases, MFSBO-CS either reaches comparably or outperforms the optimization result from various Bayesian optimization methods with only approximately one- to two-thirds of the computation cost.}, number={5}, journal={ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS}, author={Wang, Yi and Franzon, Paul D. and Smart, David and Swahn, Brian}, year={2020}, month={Oct} }
 @article{li_jiao_chou_mayder_franzon_2020, title={Self-Evolution Cascade Deep Learning Model for High-Speed Receiver Adaptation}, volume={10}, ISSN={["2156-3985"]}, DOI={10.1109/TCPMT.2020.2992186}, abstractNote={The IBIS algorithmic modeling interface (IBIS-AMI) has become the standard methodology to model Serializer/Deserializer (SerDes) behavior for end-to-end high-speed serial link simulations. Meanwhile, machine learning (ML) techniques can mimic a black-box system behavior. This article proposes the self-evolution cascade deep learning (SCDL) model to show a parallel approach to effectively modeling adaptive SerDes behavior. Specifically, the proposed self-guide learning methodology uses its own failure experiences to optimize its future solution search according to the prediction of the receiver equalization adaptation trend. The proposed SCDL model can provide the high-correlation adaptation results, while the adaptation simulation time is much faster than conventional IBIS-AMI models.}, number={6}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Li, Bowen and Jiao, Brandon and Chou, Chih-Hsun and Mayder, Romi and Franzon, Paul}, year={2020}, month={Jun}, pages={1043–1053} }
 @article{park_davis_franzon_2019, title={3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model}, volume={66}, ISSN={["1558-0806"]}, DOI={10.1109/TCSI.2018.2868901}, abstractNote={In this paper, we present 3-D-DATE, a circuit-level dynamic random access memory (DRAM) area, timing, and energy model that models both the front and back end of 3-D integrated DRAM designs from 90–16 nm, across a broader range of emerging transistor devices and through-silicon vias. This paper improves upon previous studies by providing detailed process models all the way down to the 16-nm technology node and incorporating DRAMs implemented with emerging gate transistor devices. Finally, we validate the model against both several commodity planar and 3-D DRAMs, from 80- to 30-nm process nodes, with the following metrics: energy with a mean error of 5%–1% and a standard deviation up to 9.8%, speed with a mean error of 13%–27%, and a standard deviation up to 24% and area within 3%–1% and a standard a standard deviation up to 4.2%.}, number={2}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS}, author={Park, Jong Beom and Davis, William Rhett and Franzon, Paul D.}, year={2019}, month={Feb}, pages={756–768} }
 @article{park_baker_franzon_2019, title={Appliance Identification Algorithm for a Non-Intrusive Home Energy Monitor Using Cogent Confabulation}, volume={10}, ISSN={1949-3053}, DOI={10.1109/TSG.2017.2751465}, abstractNote={This paper presents an appliance identification algorithm for use with a non-intrusive home energy monitor based on a cogent confabulation neural network. As a cogent confabulation neural network does not require multiplications during the identification phase, it is an effective choice for systems with low-computational capability. A non-intrusive home energy monitor needs to learn not only the energy patterns of individual appliances but also those of combinations of appliances. To relieve the burden of learning power patterns of the combinations, this paper proposes a parameter-building scheme based on the parameters of individual appliances. The proposed algorithm is evaluated on datasets prepared by the reference energy disaggregation dataset and the authors. The average success rate was 83.8% for up to eight appliances and showed better performance than the combinatorial optimization and artificial neural network approaches.}, number={1}, journal={IEEE Transactions on Smart Grid}, author={Park, S. W. and Baker, L. B. and Franzon, P. D.}, year={2019}, month={Jan}, pages={714–721} }
 @book{franzon_jan marinissen_s. bakir_2019, place={Weinheim, Germany}, title={Handbook of 3D Integration: Design, Test, and Thermal Management}, ISBN={9783527338559 9783527697052}, url={http://dx.doi.org/10.1002/9783527697052}, DOI={10.1002/9783527697052}, abstractNote={This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.}, publisher={Wiley}, year={2019}, month={Feb} }
 @inbook{franzon_2018, title={3D Design Styles}, booktitle={3D Handbook Design and Test}, publisher={Wiley}, author={Franzon, P.}, editor={Franzon, P. and Martissen, E. and Bakir, M.Editors}, year={2018} }
 @inbook{franzon_2018, title={3D Integration: Technology and Design}, booktitle={3D Integration in VLSI Circuits}, author={Franzon, P.}, editor={Sakuma, K.Editor}, year={2018} }
 @book{franzon_martissen_bakir_2018, title={3DIC Handbook Design and Test}, publisher={Wiley}, year={2018} }
 @inbook{franzon_2018, title={Electronic Design Automaton for 3D}, booktitle={3D Handbook Design and Test}, publisher={Wiley}, author={Franzon, P.}, editor={Franzon, P. and Martissen, E. and Bakir, M.Editors}, year={2018} }
 @article{schabel_franzon_2018, title={Exploring the Tradeoffs of Application-Specific Processing}, volume={8}, ISSN={["2156-3357"]}, DOI={10.1109/JETCAS.2018.2849939}, abstractNote={Non-traditional processing schemes continue to grow in popularity as a means to achieve high performance with greater energy-efficiency. Data-centric processing is one such scheme that targets functional-specialization and memory bandwidth limitations, opening up small processors to wide memory IO. These functional-specific accelerators prove to be an essential component to achieve energy-efficiency and performance, but purely application-specific integrated circuit accelerators have expensive design overheads with limited reusability. We propose an architecture that combines existing processing schemes utilizing CGRAs for dynamic data path configuration as a means to add flexibility and reusability to data-centric acceleration. While flexibility adds a large energy overhead, performance can be regained through intelligent mappings to the CGRA for the functions of interest, while reusability can be gained through incrementally adding general purpose functionality to the processing elements. Building upon previous work accelerating sparse encoded neural networks, we present a CGRA architecture for mapping functional accelerators operating at 500 MHz in 32 nm. This architecture achieves a latency-per-function within <inline-formula> <tex-math notation="LaTeX">$2{\times}$ </tex-math></inline-formula> of its function-specific counterparts with energy-per-operation increases between 21–188<inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula>, and energy-per-area increases between 1.8–3.6<inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula>.}, number={3}, journal={IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS}, author={Schabel, Joshua C. and Franzon, Paul D.}, year={2018}, month={Sep}, pages={531–542} }
 @article{sarkar_mills_lee_pitts_misra_franzon_2018, title={On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process}, volume={47}, ISSN={["1543-186X"]}, DOI={10.1007/s11664-017-5914-x}, number={2}, journal={JOURNAL OF ELECTRONIC MATERIALS}, author={Sarkar, Biplab and Mills, Steven and Lee, Bongmook and Pitts, W. Shepherd and Misra, Veena and Franzon, Paul D.}, year={2018}, month={Feb}, pages={994–997} }
 @article{kim_won_franzon_2017, title={Corrections to “Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding”[ Aug 13 1562-1567]}, volume={25}, ISSN={1063-8210 1557-9999}, url={http://dx.doi.org/10.1109/tvlsi.2016.2647621}, DOI={10.1109/tvlsi.2016.2647621}, abstractNote={The authors of [1] would like to note the following corrections in reference numbering. It is difficult to find correct references in the currently published paper due to the reference discords.}, number={5}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Kim, HoonSeok and Won, Chanyoun and Franzon, Paul D.}, year={2017}, month={May}, pages={1792–1792} }
 @inproceedings{srinivasan_chowdhury_forbes_widialaksono_zhang_schabel_ku_lipa_rotenberg_davis_et al._2017, title={H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor}, DOI={10.1109/ICCD.2017.30}, abstractNote={A single-ISA heterogeneous multi-core processor(HMP) [2], [7] is comprised of multiple core types that all implement the same instruction-set architecture (ISA) but have different microarchitectures. Performance and energy is optimized by migrating a thread's execution among core types as its characteristics change. Simulation-based studies with two core types, one simple (low power) and the other complex (high performance), has shown that being able to switch cores as frequently as once every 1,000 instructions increases energy savings by 50% compared to switching cores once every 10,000 instructions, for the same target performance [10]. These promising results rely on extremely low latencies for thread migration. Here we present the H3 chip that uses 3D die stacking and novel microarchitecture to implement a heterogeneous multi-core processor (HMP) with low-latency fast thread migration capabilities. We discuss details of the H3 design and present power and performance results from running various benchmarks on the chip. The H3 prototype can reduce power consumption of benchmarks by up to 26%.}, booktitle={2017 IEEE International Conference on Computer Design (ICCD)}, author={Srinivasan, V. and Chowdhury, R. B. R. and Forbes, E. and Widialaksono, R. and Zhang, Z. Q. and Schabel, J. and Ku, S. and Lipa, S. and Rotenberg, E. and Davis, W. R. and et al.}, year={2017}, pages={145–152} }
 @article{wyers_morton_sollner_kelley_franzon_2016, title={A Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing RFICs}, volume={24}, ISSN={1063-8210 1557-9999}, url={http://dx.doi.org/10.1109/TVLSI.2015.2424211}, DOI={10.1109/tvlsi.2015.2424211}, abstractNote={A generally applicable calibration technique for digitally reconfigurable self-healing radio frequency integrated circuits based on a hybrid of the Nelder-Mead and Hooke-Jeeves direct search algorithms is presented. The proposed algorithm is applied to the multiobjective problem of gain error and phase error minimization for a self-healing phase rotator test case. For the 8-D phase rotator calibration problem, we show that the proposed hybrid Nelder-Mead and Hooke-Jeeves calibration algorithm is capable of reducing the gain error and phase error of the phase rotator output to less than a maximum of 0.5 dB and 2°, respectively, relative to the chosen gain and phase targets. A 3-GHz self-healing phase rotator test chip was fabricated in a 45-nm silicon-on-insulator CMOS process, and the measured data were obtained to validate the performance of the proposed calibration algorithm.}, number={3}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Wyers, Eric J. and Morton, Matthew A. and Sollner, T. C. L. Gerhard and Kelley, C. T. and Franzon, Paul D.}, year={2016}, month={Mar}, pages={1151–1164} }
 @inproceedings{dey_franzon_2016, title={Design and ASIC acceleration of cortical algorithm for text recognition}, ISBN={9781509013678}, url={http://dx.doi.org/10.1109/socc.2016.7905447}, DOI={10.1109/socc.2016.7905447}, abstractNote={Cortical algorithms, inspired by the neocortex, promise to outperform conventional algorithms in unsupervised learning tasks, i.e. with unlabeled data. The aim of the work reported in this paper was to design and implement an application specific integrated circuit (ASIC) having a massive speedup of a cortical algorithm, as compared with a CPU baseline. This ASIC is designed to implement a scaled-down version of Sparsey, an algorithm based on structural and functional properties of the brain's cortex. The design was benchmarked on the Short Message Service (SMS) spam collection dataset from the UCI machine learning repository. It was found that the synthesis area and power consumption of a single column (i.e., mac or PE) are 0.122 mm2 and 5.15 mW using 45 nm technology and 0.171 mm2 and 7.94 mW using 65 nm technology. The processing time for a single frame was 3.075 µs (learning) and 0.675 µs (recognition). The performance speedup in learning and recognition modes of ASIC implementation was 203× and 843× times that of software implementation on a CPU based platform.}, booktitle={2016 29th IEEE International System-on-Chip Conference (SOCC)}, publisher={IEEE}, author={Dey, Sumon and Franzon, Paul D.}, year={2016}, month={Sep} }
 @inproceedings{zhao_bhanushali_franzon_2016, title={Design of a rectifier-free UHF Gen-2 compatible RFID Tag using RF-only logic}, ISBN={9781467388078}, url={http://dx.doi.org/10.1109/rfid.2016.7488013}, DOI={10.1109/rfid.2016.7488013}, abstractNote={AC-DC rectifier and storage capacitors take up 25% or more of chip area for cost-sensitive passive RFID tags. In this work, we show that these components can be eliminated by utilizing a RF-only circuit structure. Therefore, the chip would be smaller and cheaper. RF-only logic permits digital operations to be performed from an AC, rather than DC, power supply. An UHF Gen-2 compatible RFID tag is designed using the RF-only logic. Powering and communication solutions in direct ASK carrier powered scenario are developed. RF front-end circuits are designed in RF-only fashion and a standard cell library of RF-only logic is developed and tailored for this application. The RFID tag is implemented in a 0.13 μm CMOS technology. The tag dimensions are 0.6 mm × 0.3 mm and its sensitivity is 0 dBm at RF amplitude of 500mV in simulation. The same methodology can be applied to enable lower RF amplitude implementations that trade off area for sensitivity.}, booktitle={2016 IEEE International Conference on RFID (RFID)}, publisher={IEEE}, author={Zhao, Wenxu and Bhanushali, Kirti and Franzon, Paul}, year={2016}, month={May} }
 @inproceedings{li_franzon_2016, title={Hardware implementation of Hierarchical Temporal Memory algorithm}, ISBN={9781509013678}, url={http://dx.doi.org/10.1109/socc.2016.7905453}, DOI={10.1109/socc.2016.7905453}, abstractNote={In this paper, a hardware ASIC implementation of the Numenta Hierarchical Temporal Memory (HTM) algorithm is presented. Each column in the neural network is implemented as a processing element (PE). Neuron cells in columns are built as identical cell modules. Dedicated register files for each module cell are employed to replace the conventional centralized memory organization. A complete neural network is built as a matrix of PEs connected in the mesh network. Both first order and high order network are successfully performed on a 20×20 PE matrix using images from MNIST dataset as input patterns. The power and area of a single PE including 2 cell modules are 1.29 mW and 17511 µm2 respectively. The average processing time in the proposed implementation is 4.52 µs in learning mode and 4.39 µs in inference mode. Compared to the performance of a software implementation on the 4 threads CPU, the ASIC version provides a 329.6× speedup in learning mode.}, booktitle={2016 29th IEEE International System-on-Chip Conference (SOCC)}, publisher={IEEE}, author={Li, Weifu and Franzon, Paul}, year={2016}, month={Sep} }
 @inproceedings{li_franzon_2016, title={Machine learning in physical design}, ISBN={9781509061105}, url={http://dx.doi.org/10.1109/epeps.2016.7835438}, DOI={10.1109/epeps.2016.7835438}, abstractNote={Machine learning, a powerful technique for building models, can rapidly provide accurate predictions. Since Integrated Circuit (IC) design and manufacturing have tremendously high complexity and enormous data, there is a surge in adapting machine learning approach in IC Design stages, as machine learning can provide fast predictions. Recently, machine learning has been used in some IC Design stages (e.g. Physical Verification), but not in Physical Design. In this research, machine learning is adapted to Physical Design. Surrogate Modeling is implemented to predict results after GR in Physical Design. Machine learning models for predicting Detailed Route (DR) results using Global Route (GR) results are also discussed. With surrogate models and machine learning methods, circuit performances after Physical Design (e.g. hold violation check and area) would be predicted quickly.}, booktitle={2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)}, publisher={IEEE}, author={Li, Bowen and Franzon, Paul D.}, year={2016}, month={Oct} }
 @article{yan_aygun_braunisch_franzon_2016, title={Multimode High-Density Link Design Methodology and Implementation}, volume={6}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2016.2585498}, abstractNote={As higher density of interconnects and packages is demanded, crosstalk noise is becoming more important. Multimode or modal signaling offers the ability to improve wiring density with significantly reduced crosstalk by coding the signals using fundamental modes of propagation only. Past work has demonstrated this on uniform channels. This paper presents a design methodology for designing practical nonuniform high density links using multimode signaling. A channel that consists of printed circuit board (PCB) and package routing, and vertical interconnects is designed to achieve highest density and low crosstalk-induced jitter. Compared to the baseline benchmark channel, the optimized channel demonstrates 4×, 4×, and 2× density improvement of PCB and package vertical and package horizontal routing, respectively, and at the same time achieves a 42% RMS jitter reduction. This new approach significantly improves the ability to design high-density low-crosstalk interconnect subsystems in practical scenarios.}, number={8}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Yan, Zhuo and Aygun, Kemal and Braunisch, Henning and Franzon, Paul D.}, year={2016}, month={Aug}, pages={1251–1260} }
 @inproceedings{harris_davis_franzon_2016, title={Novel packaging and thermal measurement for 3D heterogeneous stacks}, ISBN={9781509029402}, url={http://dx.doi.org/10.1109/3dpeim.2016.7570543}, DOI={10.1109/3dpeim.2016.7570543}, abstractNote={Presents a collection of slides covering the following topics: packaging; thermal measurement: 3D heterogeneous stacks; heterogeneous integration; chip analysis; NCSU thermal test vehicle; EFFP thermal property extraction; bonding; calibration; HEMT; CMOS and air bridge metal measurement.}, booktitle={2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)}, publisher={IEEE}, author={Harris, T. Robert and Davis, W. Rhett and Franzon, Paul}, year={2016}, month={Jun} }
 @inproceedings{widialaksono_basu roy chowdhury_zhang_schabel_lipa_rotenberg_rhett davis_franzon_2016, title={Physical design of a 3D-stacked heterogeneous multi-core processor}, ISBN={9781509013999}, url={http://dx.doi.org/10.1109/3dic.2016.7970036}, DOI={10.1109/3dic.2016.7970036}, abstractNote={With the end of Dennard scaling, three dimensional stacking has emerged as a promising integration technique to improve microprocessor performance. In this paper we present a 3D-SIC physical design methodology for a multi-core processor using commercial off-the-shelf tools. We explain the various flows involved and present the lessons learned during the design process. The logic dies were fabricated with GlobalFoundries 130 nm process and were stacked using the Ziptronix face-to-face (F2F) bonding technology. We also present a comparative analysis which highlights the benefits of 3D integration. Results indicate an order of magnitude decrease in wirelengths for critical inter-core components in the 3D implementation compared to 2D implementations.}, booktitle={2016 IEEE International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Widialaksono, Randy and Basu Roy Chowdhury, Rangeen and Zhang, Zhenqian and Schabel, Joshua and Lipa, Steve and Rotenberg, Eric and Rhett Davis, W. and Franzon, Paul}, year={2016}, month={Nov} }
 @inproceedings{schabel_baker_dey_li_franzon_2016, title={Processor-in-memory support for artificial neural networks}, ISBN={9781509013708}, url={http://dx.doi.org/10.1109/icrc.2016.7738697}, DOI={10.1109/icrc.2016.7738697}, abstractNote={Hardware acceleration of artificial neural network (ANN) processing has potential for supporting applications benefiting from real time and low power operation, such as autonomous vehicles, robotics, recognition and data mining. Most interest in ANNs targets acceleration of deep multi-layered ANNs that can require days of offline training to converge on a desired network behavior. Interest has grown in ANNs capable of supporting unsupervised training, where networks can learn new information from unlabeled data dynamically without the need for offline training. These ANNs require large memories with bandwidths much higher than supported in modern GPGPUs. Custom hardware acceleration and memory co-design holds the potential to provide real-time performance in cases where the performance requirements cannot be met by modern GPGPUs. This work presents a custom processor solution to accelerate two hetero-associative memories (Sparsey and HTM) capable of unsupervised and one-hot learning. This custom processor is implemented as an expandable ASIP built upon a configurable SIMD engine for exploiting parallelism. Functional specialization is implemented utilizing processor-in-memory techniques, which results in up to a 20× speedup and a 2000× reduction in energy per frame compared to a software implementation operating on a dataset for recognition of human actions.}, booktitle={2016 IEEE International Conference on Rebooting Computing (ICRC)}, publisher={IEEE}, author={Schabel, Joshua and Baker, Lee and Dey, Sumon and Li, Weifu and Franzon, Paul D.}, year={2016}, month={Oct} }
 @inproceedings{nigussie_franzon_2016, title={RDL and interposer design for DiRAM4 interfaces}, ISBN={9781509061105}, url={http://dx.doi.org/10.1109/epeps.2016.7835408}, DOI={10.1109/epeps.2016.7835408}, abstractNote={This paper presents results of signal integrity study conducted on two packaging designs: redistribution layer (RDL) for face-to-face stacking and 2.5D interposer for lateral connection of four processor chips with high performance memory die having a bandwidth of 4Tb/s.}, booktitle={2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)}, publisher={IEEE}, author={Nigussie, Theodros and Franzon, Paul D.}, year={2016}, month={Oct} }
 @inproceedings{harris_pavlidis_wyers_newberry_graham_franzon_davis_2016, title={Thermal raman and IR measurement of heterogeneous integration stacks}, DOI={10.1109/ITHERM.2016.7517727}, abstractNote={Thermal management and planning is important for heterogeneous integration due to the introduction of a complex thermal path. Thermal measurement of operating devices provides necessary data points for future design as well as validation of models. In this paper, two methods for measuring thermal performance of DAHI (Diverse Accessible Heterogeneous Integration) GaN HEMTs are presented and contrasted: IR microscopy and micro Raman spectroscopy. The QFI IR system uses a per-pixel material emissivity flat temperature calibration when the device is in an off-state, and then calculates operating temperatures by CCD exposure. Two separate QFI systems with differing CCD resolutions were used to collect thermal data and are compared. Raman Thermometry by contrast, is a laser point measurement of the frequency shift in scattered photons due to phonon vibrational modes whose frequencies are temperature dependent. Differences in measurements between the two methods arising from the stack of materials used in the DAHI process and their transparency are discussed. A method for measuring the surface temperature of the devices through Raman by the use of TiO2 nanoparticles is also presented in conjunction with a profile of the HEMT. Measurements are presented alongside thermal simulation results using prototype software Mentor Graphics™ Calibre®.}, booktitle={2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)}, author={Harris, T. R. and Pavlidis, G. and Wyers, E. J. and Newberry, D. M. and Graham, S. and Franzon, P. and Davis, W. R.}, year={2016}, pages={1505–1510} }
 @article{charles_franzon_2015, title={A Multitier Study on Various Stacking Topologies of TSV-Based PDN Systems Using On-Chip Decoupling Capacitor Models}, volume={5}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2015.2416196}, abstractNote={We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networks (PDNs) for hierarchical on-die simulation and interconnect noise analysis. This paper compares the quality of power delivery in 3-D stacking scenarios for three distinct chip stacking topologies: 1) face-to-back (F2B); 2) face-to-face (F2F); and 3) back-to-back (B2B). Quantitatively, this paper compared the impedance noise level between the three stacking topologies and found the PDN impedance noise of F2F chip stacking to be relatively lower than F2B and B2B chip stacking topologies. A power delivery impedance below 1 Ω for F2F chip stacking topology was possible up to 2 GHz. However, for F2B and B2B chip stacking, the PDN impedance could not get beyond sub-1 Ω. The impedance was simulated between 0.1 and 20 GHz. Among power grid and power and ground TSV models presented in this paper, we also present and implemented a metal-insulator-metal capacitor model written as a complex impedance equation. With capacitor dimensions similar to the unit cell gird size (200 μm × 200 μm), the capacitance density (per unit area) ranged from 0.062 pF/μm2 to 5.325 fF/μm2.}, number={4}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Charles, Gary and Franzon, Paul D.}, year={2015}, month={Apr}, pages={541–550} }
 @inproceedings{wyers_harris_massad_franson_2015, title={Characterization of the Mechanical Stress Impact on Device Electrical Performance in the CMOS and III-V HEMT/HBT Heterogeneous Integration Environment}, booktitle={Proceedings Gomactech 2015}, author={Wyers, E.J. and Harris, T.R. and Massad, J.E. and Franson, P.D.}, year={2015}, month={Mar} }
 @inproceedings{wyers_harris_pitts_massad_franzon_2015, title={Characterization of the mechanical stress impact on device electrical performance in the CMOS and III–V HEMT/HBT heterogeneous integration environment}, ISBN={9781467393850}, url={http://dx.doi.org/10.1109/3dic.2015.7334597}, DOI={10.1109/3dic.2015.7334597}, abstractNote={The stress impact of the CMOS and III-V heterogeneous integration environment on device electrical performance is being characterized. Measurements from a partial heterogeneous integration fabrication run will be presented to provide insight into how the backside source vias, alternatively referred to as through-silicon-carbide vias (TSCVs), used within the heterogeneous integration environment impacts GaN HEMT device-level DC performance.}, booktitle={2015 International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Wyers, Eric J. and Harris, T. Robert and Pitts, W. Shep and Massad, Jordan E. and Franzon, Paul D.}, year={2015}, month={Aug} }
 @inbook{franzon_swaminathan_2015, edition={Second}, title={Chip Package Codesign}, booktitle={The Handbook for EDA of Electronic Circuits}, publisher={CRC Press}, author={Franzon, P. and Swaminathan, M.}, editor={Scheffer, Lou and Lavagno, Luciano and Martin, GrantEditors}, year={2015} }
 @inproceedings{franzon_rotenberg_tuck_davis_zhou_schabel_zhang_dwiel_forbes_huh_et al._2015, title={Computing in 3D}, ISBN={9781479986828}, url={http://dx.doi.org/10.1109/cicc.2015.7338401}, DOI={10.1109/cicc.2015.7338401}, abstractNote={3D technologies offer significant potential to improve total performance and performance per unit of power. After exploiting TSV technologies for cost reduction and increasing memory bandwidth, the next frontier is to create sophisticated logic on logic solutions that promise further increases in performance/power beyond those attributable to memory interfaces alone. These include heterogeneous integration for computing and exploitation of the high amounts of 3D interconnect available to reduce total interconnect power. Challenges include access for prototype quantities and the design of sophisticated static and dynamic thermal management methods and technologies, as well as test.}, booktitle={2015 IEEE Custom Integrated Circuits Conference (CICC)}, publisher={IEEE}, author={Franzon, Paul and Rotenberg, Eric and Tuck, James and Davis, W. Rhett and Zhou, Huiyang and Schabel, Joshua and Zhang, Zhenquian and Dwiel, J. Brandon and Forbes, Elliott and Huh, Joonmoo and et al.}, year={2015}, month={Sep} }
 @inproceedings{franzon_rotenberg_davis_tuck_davis_zhou_schabel_zhang_dwiel_forbes_et al._2015, place={Singapore}, title={Computing in 3D}, ISBN={9781467393850}, url={http://dx.doi.org/10.1109/3dic.2015.7334571}, DOI={10.1109/3dic.2015.7334571}, abstractNote={3DIC technology refers to stacking and interconnecting chips and substrates (“interposers”) with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. We have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Possible extensions to Cortical Processing are discussed.}, booktitle={2015 International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Franzon, Paul D. and Rotenberg, Eric and Davis, W. Rhett and Tuck, James and Davis, W. Rhett and Zhou, Huiyang and Schabel, Joshua and Zhang, Zhenquian and Dwiel, J. Brandon and Forbes, Elliott and et al.}, year={2015}, month={Aug} }
 @inproceedings{franzon_2015, title={Defense Applications of 3DIC}, booktitle={Proceedings Gomactech 2015}, author={Franzon, P.}, year={2015}, month={Mar} }
 @inbook{wyers_kelley_franzon_2015, title={Optimization for Self-Calibrating Circuits}, booktitle={Semiconductor Devices in Harsh Conditions}, publisher={CRC}, author={Wyers, Eric and Kelley, Tim and Franzon, Paul}, year={2015} }
 @inproceedings{harris_wyers_wang_graham_pavlidis_franzon_davis_2015, title={Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks}, ISBN={9781467393850}, url={http://dx.doi.org/10.1109/3dic.2015.7334616}, DOI={10.1109/3dic.2015.7334616}, abstractNote={Integration of materials such as GaN, InP, SiGe, and Si is a natural extension of the 3D-IC perspective and provides a unique solution for high performance circuits. In this approach, application of a component is no longer dependent on semiconductor material selection. In this paper, preliminary results are presented which examine the thermal performance of the technology. A thermal analysis prototype solution in Mentor Graphics™ Calibre® provides surface heat maps based on IC layout, material property, and geometric configuration files. Chiplets are connected by heterogeneous interconnect (HIC). Differences in thermal performance of GaN and InP chiplets are explored by varying the number of HICs. Two methods for building up the model of a test chip are compared. One method uses custom scripts to place discrete blocks in the model to represent HICs, while the other uses thermal material properties extracted from the layout. Measurements presented confirm simulated results.}, booktitle={2015 International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Harris, T. Robert and Wyers, Eric J. and Wang, Lee and Graham, Samuel and Pavlidis, Georges and Franzon, Paul D. and Davis, W. Rhett}, year={2015}, month={Aug}, pages={1–3} }
 @inproceedings{franzon_rotenberg_tuck_zhou_davis_dai_huh_ku_lipa_li_et al._2014, title={3D-enabled customizable embedded computer (3DECC)}, ISBN={9781479984725}, url={http://dx.doi.org/10.1109/3dic.2014.7152143}, DOI={10.1109/3dic.2014.7152143}, abstractNote={This paper describes a 3D computer architecture designed to achieve the lowest possible power consumption for “embedded applications” like radar and signal processing. It introduces several unique concepts including a low-power SIMD tile, low-power 3D memories, and 3D and 2.5D interconnect that is circuit switched so it can be tuned at run-time for a specific application. When conservatively projected to the 7 nm node, simulations of the architecture show potential for exceeding 75 GFLOPS/W, about 20x better than today's CPUs and GPUs. This translates to 13 pJ/FLOP. This paper will focus on the 3D specific aspects of the design. This architecture is highly suited to DSP and multimedia workflows.}, booktitle={2014 International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Franzon, Paul D. and Rotenberg, Eric and Tuck, James and Zhou, Huiyang and Davis, W. Rhett and Dai, Hongwen and Huh, Joonmoo and Ku, Sunkgwan and Lipa, Steve and Li, Chao and et al.}, year={2014}, month={Dec} }
 @inproceedings{karim_franzon_2014, title={A 0.65 mW/Gbps 30 Gbps capacitive coupled 10 mm serial link in 2.5D silicon interposer}, ISBN={9781479936410 9781479936434}, url={http://dx.doi.org/10.1109/epeps.2014.7103614}, DOI={10.1109/epeps.2014.7103614}, abstractNote={A multi-capacitor coupled signaling structure is employed to enable low-power high frequency communications in 10 mm long interposer traces. On-chip Metal-Insulator-Metal (MIM) capacitor was used to implement the Multi capacitor structure. A continuous time feed forward tunable capacitive equalization was used to compensate for the frequency dependent losses. The multi-capacitor structure is used to implement a low power equalizer. 10 mm long, 10 μm pitch and 1 μm thick differential interposer traces were used in a two metal layer stack as the channel. A pulse receiver is presented which can recover 30 Gbps/channel with BER better than 10-13. Using this low power design in 65 nm CMOS technology, 0.65 mW/Gbps power efficiency and 3 Gbps/μm bandwidth density were achieved.}, booktitle={2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems}, publisher={IEEE}, author={Karim, M Ataul and Franzon, Paul D.}, year={2014}, month={Oct} }
 @article{bapat_franzon_fastow_2014, title={A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory}, volume={22}, ISSN={1063-8210}, DOI={10.1109/tvlsi.2013.2296526}, abstractNote={This paper describes a scalable hardware accelerator for speech recognition, which uses a two pass decoding algorithm with word dependent N-best Viterbi Beam Search. The observation probability calculation (Senone scoring) and first pass of decoding using a Bigram language model is implemented in hardware. The word lattice output from the first pass is used by software for the second pass, with a trigram language model. The proposed design uses a logic-on-memory approach to make use of high bandwidth nor flash memory to improve random read performance for Senone scoring and first pass decoding, both of which are memory intensive operations. The proposed HW/SW co-design achieves an overall speed up of 4.3X over a 2.4-GHz Intel Core 2 Duo processor running the CMU Sphinx speech recognition software, while consuming an estimated 1.72 W of power. The hardware accelerator provides improved speech recognition accuracy by supporting larger acoustic models and word dictionaries while maintaining real-time performance.}, number={12}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, author={Bapat, O. A. and Franzon, P. D. and Fastow, R. M.}, year={2014}, month={Dec}, pages={2701–2712} }
 @article{chen_zhu_davis_franzon_2014, title={Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits}, volume={4}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2014.2361356}, abstractNote={In this paper, we present novel techniques to handle the complexity and challenges in clock distribution for 3-D integrated circuit. First, we propose a novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry. The new deskew technique neither relies on an accurate through-silicon-vias model nor an accurate reference clock distribution. Second, we design a phase-mixer-based tunable-delay-buffer (TDB), which can be linearly tuned in 360° and tolerant to process-voltage-termperature (PVT) variations. Third, based on the new deskew technique and TDB design, we propose an efficient clock distribution network topology, which can be realized without a need of balanced H-tree. Moreover, a thermal profile-based optimization flow is developed to further improve the power efficiency and reduce design overhead. A case study shows that the proposed techniques are able to largely improve the clock skews. The optimization flow is capable of reducing the design cost to achieve a better tradeoff of the skew performance and the design overhead.}, number={11}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Chen, Xi and Zhu, Ting and Davis, William Rhett and Franzon, Paul D.}, year={2014}, month={Nov}, pages={1862–1870} }
 @inproceedings{franzon_grivet-talocia_2014, title={Advances in TSVs and 3D interconnects}, ISBN={9781479936410 9781479936434}, url={http://dx.doi.org/10.1109/epeps.2014.7103590}, DOI={10.1109/epeps.2014.7103590}, abstractNote={A record of the panel discussion was not made available for publication as part of the conference proceedings.}, booktitle={2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems}, publisher={IEEE}, author={Franzon, Paul and Grivet-Talocia, Stefano}, year={2014}, month={Oct} }
 @article{sarkar_ramanan_jayanti_di spigna_lee_franzon_misra_2014, title={Dual Floating Gate Unified Memory MOSFET With Simultaneous Dynamic and Non-Volatile Operation}, volume={35}, ISSN={["1558-0563"]}, DOI={10.1109/led.2013.2289751}, abstractNote={Dual floating gate flash memory has been fabricated and characterized to show dynamic operation, non-volatile operation, and simultaneous dynamic and non-volatile operation. The gate stack consists of a thin dielectric separating two floating gates sandwiched between a tunnel dielectric and interpoly dielectric. The quality of the thin dielectric that separates the floating gates is of utmost importance to retain dynamic operation. In this letter, we investigate a dual floating gate memory transistor and show its potential to combine DRAM and flash functionality in the same device.}, number={1}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Sarkar, Biplab and Ramanan, Narayanan and Jayanti, Srikant and Di Spigna, Neil and Lee, Bongmook and Franzon, Paul and Misra, Veena}, year={2014}, month={Jan}, pages={48–50} }
 @inproceedings{widialaksono_zhao_davis_franzon_2014, title={Leveraging 3D-IC for on-chip timing uncertainty measurements}, ISBN={9781479984725}, url={http://dx.doi.org/10.1109/3dic.2014.7152172}, DOI={10.1109/3dic.2014.7152172}, abstractNote={Modern high-performance designs require accurate on-chip timing uncertainty measurements for post-silicon validation of high speed interfaces and clock distribution networks. On-chip timing measurements capabilities must keep up with growing design complexity and process variations to meet competitive product time-to-market. However, enhancing silicon debug capabilities cannot simply be met by proliferating on-chip structures, since the overhead would be prohibitively expensive to deploy. We propose moving on-chip debug and validation structures onto a separate die which would be stacked onto the product die using three-dimensional integration (3D-IC). This paper focuses on achieving observability at clock sinks which are critical for understanding on-chip timing uncertainty. We present a circuit implementation and design flow which realizes high volume on-chip timing measurements for a 2D product die.}, booktitle={2014 International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Widialaksono, Randy and Zhao, Wenxu and Davis, W. Rhett and Franzon, Paul}, year={2014}, month={Dec} }
 @article{gadfort_franzon_2014, title={Millimeter-Scale True 3-D Antenna-in-Package Structures for Near-Field Power Transfer}, volume={4}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2014.2349983}, abstractNote={This paper describes the modeling, fabrication, and measurement of a method to construct true 3-D antennas for radio frequency (RF) power harvesting in millimeter-scale sensors. The goal is to create an omnidirectional RF power-harvesting structure, which can provide power even if the sensor and external power source are not perfectly aligned. Because the orientation of the sensor is not known in advance, the antenna must work equally well in all directions. To realize such a structure, antennas will be built into the packaging of the sensor, and this allows for the largest possible antenna without increasing the size of the sensor and by combining antennas which are orthogonal to each other. This construction results in a cubic structure, where the power-transfer efficiency can be increased by 22 dB over a traditional single-coil setup at the worst case orientations for the sensor. The presented structures will range from 3 to 5 mm cubes.}, number={10}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Gadfort, Peter and Franzon, Paul D.}, year={2014}, month={Oct}, pages={1574–1581} }
 @inproceedings{priyadarshi_davis_franzon_2014, title={Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC}, ISBN={9781479921539}, url={http://dx.doi.org/10.1109/icicdt.2014.6838612}, DOI={10.1109/icicdt.2014.6838612}, abstractNote={Three dimensional integration technologies offer significant potential to improve performance, performance per unit power and integration density. However, increased power density and thermal resistances leading to higher on-chip temperature is imposing several implementation challenges and restricting widespread adaptation of this technology. This necessitates the need for CAD flows and tools facilitating early thermal evaluation of possible 3D design choices and thermal management techniques. This paper presents a CAD flow and associated framework called Pathfinder3D, which facilitates physically-aware system-level thermal simulation of 3DICs. Usage of Pathfinder3D is shown using a case study comparing thermal profiles of 2D and three 3D implementations of a quadcore chip multiprocessor.}, booktitle={2014 IEEE International Conference on IC Design & Technology}, publisher={IEEE}, author={Priyadarshi, Shivam and Davis, W. Rhett and Franzon, Paul D.}, year={2014}, month={May} }
 @inbook{burr_franzon_2014, title={Storage Class Memories}, booktitle={Emerging Nanoelectronic Devices}, publisher={Wiley}, author={Burr, G. and Franzon, P.}, editor={Chen, An and Hutchby, J. and Zhrinov, V. and Bourianoff, G.Editors}, year={2014} }
 @article{priyadarshi_davis_steer_franzon_2014, title={Thermal Pathfinding for 3-D ICs}, volume={4}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2014.2321005}, abstractNote={System architects traditionally use high-level models of component blocks to predict trends for various design metrics. However, with continually increasing design complexity and a confusing array of manufacturing choices, system-level design decisions cannot be made without considering physical-level details. This effect is more pronounced for 3-D integrated circuits (ICs) because it provides a plethora of physical-level design choices, such as the number of stacking layers and the type of 3-D bonding method, along with the choices provided by 2-D ICs. Thus, it is necessary for system-level flows to predict the complex interactions among system performance, power, temperature, floorplanning, process technology, computer architecture, and software/workloads. This is often called pathfinding. This paper presents a pathfinding flow that integrates SystemC transaction-level electrical and dynamic thermal simulations. The goal of this flow is to pass complex physical constraints to system architects in a convenient form. The applicability of the proposed flow is shown using an example stacking of two processor cores and L2 cache in two-tier 3-D stack.}, number={7}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Priyadarshi, Shivam and Davis, W. Rhett and Steer, Michael B. and Franzon, Paul D.}, year={2014}, month={Jul}, pages={1159–1168} }
 @inproceedings{harris_franzon_davis_wang_2014, title={Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits}, ISBN={9781479984725}, url={http://dx.doi.org/10.1109/3dic.2014.7152182}, DOI={10.1109/3dic.2014.7152182}, abstractNote={The DAPRA Diverse Accessible Heterogeneous Integration (DAHI) initiative seeks to build capability in production of integrated semiconductor circuits of differing materials. Integration of materials such as GaN, InP, SiGe, and Si is a natural extension of the 3D-IC perspective and provides a unique solution for high performance circuits. In this approach, application of a component is no longer dependent on semiconductor material selection. In this paper, preliminary results are presented which examine the thermal performance of the technology. A thermal analysis prototype solution in Mentor Graphics® Calibre® provides surface heat maps based on IC layout, material property, and geometric configuration files. Chiplets are connected by heterogeneous interconnect (HIC). Differences in thermal performance of GaN and InP chiplets are explored by varying the number of HICs. Two methods for building up the model of a test chip are compared. One method automatically places discrete blocks in the model to represent HICs, while the other uses thermal material properties extracted from the layout.}, booktitle={2014 International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Harris, T. Robert and Franzon, Paul and Davis, W. Rhett and Wang, Lee}, year={2014}, month={Dec} }
 @article{wyers_steer_kelley_franzon_2013, title={A Bounded and Discretized Nelder-Mead Algorithm Suitable for RFIC Calibration}, volume={60}, ISSN={["1558-0806"]}, DOI={10.1109/tcsi.2012.2230496}, abstractNote={This paper describes a calibration technique for noisy and nonconvex circuit responses based on the Nelder-Mead direct search algorithm. As Nelder-Mead is intended for unconstrained optimization problems, we present an implementation of the algorithm which is suitable for bounded and discretized RFIC calibration problems. We apply the proposed algorithm to the problem of spurious tone reduction via VCO control line ripple minimization for a PLL operating at a frequency of 12 GHz. For this nonconvex calibration test case, we show that a gradient descent-based algorithm has difficulty in reducing the VCO control line ripple, while the proposed algorithm reduces the relative power of the first harmonic reference spurs by at least 10 dBc and effectively enables design complexity reduction in the supporting analog calibration circuitry.}, number={7}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS}, author={Wyers, Eric J. and Steer, Michael B. and Kelley, C. T. and Franzon, Paul D.}, year={2013}, month={Jul}, pages={1787–1799} }
 @inproceedings{zhao_gadfort_erickson_franzon_2013, title={A compact inductively coupled connector for mobile devices}, DOI={10.1109/ectc.2013.6575919}, abstractNote={A nested inductive connector, consisting of a single power channel and one or more data channels, is proposed as replacement for legacy conductive connectors in mobile devices. Advantages include minimized space in the mobile device, waterproofing, orientation independence, and resistance to stress through a breakaway mechanism. A simulation and analysis of relevant parameters, such as the transfer coefficients for both the power and data channels as well as crosstalk, of the connector design for a simple 2-layer PCB is presented. As an example, the proposed connector is utilized as a replacement for a standard TRS headphone jack found on many mobile devices. The connect or features an AC to DC rectifier, data transmitting circuits, as well as a Class-D power amplifier to drive a pair of headphones.}, booktitle={2013 IEEE 63rd Electronic Components and Technology Conference (ECTC)}, author={Zhao, W. X. and Gadfort, P. and Erickson, E. and Franzon, Paul}, year={2013}, pages={2385–2390} }
 @inproceedings{franzon_rotenberg_tuck_davis_zhou_schabel_zhang_park_dwiel_forbes_et al._2013, title={Applications and design styles for 3DIC}, ISBN={9781479923069}, url={http://dx.doi.org/10.1109/iedm.2013.6724717}, DOI={10.1109/iedm.2013.6724717}, abstractNote={3D technologies offer significant potential to improve raw performance and performance per unit power. After exploiting TSV technologies for cost reduction and increasing memory bandwidth, the next frontier is to create more sophisticated solutions that promise further increases in power/performance beyond those attributable to memory interfaces alone. These include heterogeneous integration and exploitation of the high amounts of interconnect available to provide for customization. Challenges include the creation of physical standards and the design of sophisticated static and dynamic thermal management methods.}, booktitle={2013 IEEE International Electron Devices Meeting}, publisher={IEEE}, author={Franzon, P.D. and Rotenberg, E. and Tuck, J. and Davis, W.R. and Zhou, H. and Schabel, J. and Zhang, Z. and Park, J. and Dwiel, B. and Forbes, E. and et al.}, year={2013}, month={Dec} }
 @inproceedings{yan_franzon_aygun_braunisch_2013, title={Circuit/channel co-design methodology for multimode signaling}, DOI={10.1109/ectc.2013.6575750}, abstractNote={As higher density of interconnects and packages are demanded, crosstalk noise is becoming more important in input/output (I/O) design. The multimode signaling scheme offers effective crosstalk cancellation in high density links. This paper presents a new circuit/channel co-design methodology for high density links with multimode signaling. A detailed design approach is introduced and a detailed channel design optimization example is provided to validate this method. The optimized channel shows over 60% root mean square (RMS) jitter reduction compared with single-ended signaling. The printed circuit board (PCB) and package routing density of the optimized channel are 300% and 97% higher compared with a practical benchmark channel, respectively, and still shows 31% jitter reduction.}, booktitle={2013 IEEE 63rd Electronic Components and Technology Conference (ECTC)}, author={Yan, Z. and Franzon, Paul and Aygun, K. and Braunisch, H.}, year={2013}, pages={1356–1361} }
 @article{kim_won_franzon_2013, title={Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding}, volume={21}, ISSN={["1063-8210"]}, DOI={10.1109/tvlsi.2012.2213281}, abstractNote={A new implementation approach to cancel crosstalk using modal decomposition on a multiconductor transmission bundle is presented. The proposed approach requires a CODEC only at the transmitter, not at both the transmitter and receiver. This gives potential for more flexibility, lower power, better scaling, and ease of implementation. A circuit is presented along with the simulation results.}, number={8}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Kim, HoonSeok and Won, Chanyoun and Franzon, Paul D.}, year={2013}, month={Aug}, pages={1562–1567} }
 @inproceedings{franzon_2013, title={Design and test of 2.5D and 3D stacked ICs}, ISBN={9781479907076 9781479907052}, url={http://dx.doi.org/10.1109/epeps.2013.6703444}, DOI={10.1109/epeps.2013.6703444}, abstractNote={Three dimensional chips stacked using Through Silicon Via (TSV) technology has been under consideration and the subject of intensive research for several years now. Soon the technologies will become available through standard fabs. Will the technology be an instant hit, a niche, or a flop? What is needed to ensure it reaches hit status? What are the basic manufacturing steps and flows? This tutorial will discuss these question mainly in the context of the opportunities and challenges that face the designer. What are the significant opportunities presented by 3DIC? What problems will the designer face that will need clever solutions? What are the potential solution paths?}, booktitle={2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems}, publisher={IEEE}, author={Franzon, Paul}, year={2013}, month={Oct} }
 @inproceedings{suh_franzon_2013, title={Design of 60 GHz contact less probe system for RDL in passive silicon interposer}, DOI={10.1109/3dic.2013.6702352}, abstractNote={A probe design for detecting discontinuities of a redistribution layer (RDL) on TSV silicon interposer is presented in this paper. The probe is a 60 GHz contactless system based on a quarter-wavelength directional coupler, using the capacitive coupling effects between two signal traces. The probes consists of one ground plane and one signal trace embedded in BCB, low dielectric constant insulator. The length, width, and thickness of the contactless probe are 749.3 um, 100.584 um, and 10.414 um, respectively. A time-domain reflectometery (TDR) pulse with 10 ps rise time makes it possible to obtain high resolution. A variation of the probe's TDR signal through two capacitance coupling effects indicates the location of the open or short circuit fault where RDL has. Reaching a peak and dip of the probe's TDR signal represents the open and short circuit sites, respectively.}, booktitle={2013 ieee international 3d systems integration conference (3dic)}, author={Suh, E. J. and Franzon, Paul}, year={2013} }
 @inproceedings{tshibangu_franzon_rotenberg_davis_2013, title={Design of controller for L2 cache mapped in Tezzaron stacked DRAM}, DOI={10.1109/3dic.2013.6702397}, abstractNote={3DIC technology allows implementation of fast and dense memory by allowing multiple layers of DRAM to be fabricated in a single die called Die-stacking technology. This creates opportunity to explore usage of DRAM as fast last level cache by exploiting mapping of data and tag in the same bank. This Paper investigates the implementation of such a cache controller using 3-layer 256 MB Tezzaron Octopus stacked DRAM. This memory provides a fast data access through burst-4 and burst-8 mode. To avoid multiple row activation, the entire set is confined in one row of 2KB. For a 64B cache block, 32 lines of data can be obtained in one row. In this design, only two cache blocks are used for tag while 30 blocks are used for data yielding a 30-way set associative L2 cache. Given the performance of Tezzaron memory, a low hit time of approximately 20 cycles was achieved. This hit latency includes precharge and row activation delays. This access latency was used in Gem5 full-system simulator to estimate the performance compared to a standard 2D SRAM L2 cache. An average of 15% on performance is achieved on different benchmarks while providing an average 27% on energy saving.}, booktitle={2013 IEEE International 3D Systems Integration Conference (3DIC)}, author={Tshibangu, N. M. and Franzon, P. D. and Rotenberg, E. and Davis, W. R.}, year={2013}, month={Oct} }
 @inproceedings{franzon_priyadarshi_lipa_davis_thorolfsson_2013, title={Exploring early design tradeoffs in 3DIC}, DOI={10.1109/iscas.2013.6571901}, abstractNote={This The key to gaining substantial benefit from the use of 3DIC technology is to create 3D specific designs that do more than recast a 2D optimal design into the third dimension. This paper explores some of the approaches to creating 3D specific designs and the CAD tools that can help in that exploration. The power advantages of 3D design are illustrated in details. Results from different partitioning approaches (function, modular and circuit) are presented, together with early results from a thermal pathfinding tool.}, booktitle={2013 IEEE International Symposium on Circuits and Systems (ISCAS)}, author={Franzon, P. D. and Priyadarshi, S. and Lipa, S. and Davis, W. R. and Thorolfsson, T.}, year={2013}, pages={545–549} }
 @inproceedings{zhang_noia_chakrabarty_franzon_2013, title={Face-to-face bus design with built-in self-test in 3D ICS}, DOI={10.1109/3dic.2013.6702395}, abstractNote={This paper presents a bus structure, synchronization and test scheme for fast data transfer between logic dies in stacked 3D ICs using face-to-face (F2F) micro-bumps. The proposed design permits different designs, such as microprocessor, co-processor and accelerator, to be integrated together vertically with high bandwidth and low power, which is uniquely enabled by the dense F2F micro-bumps. We propose a new teleport-register-file structure and corresponding clock gating and switching techniques to synchronize data across multiple clock domains. Simultaneous bi-directional transfer is supported and 50% reduction of flip-flops compared with conventional synchronizer design. Moreover, a lightweight built-in-self-test (BIST) unit is integrated into the bus. The BIST unit allows for rapid stuck-at and transition fault testing of the 3D bus interconnects and associated logic, without the need for an external tester. BIST allows field testing and test/validation at later stages of 3D integration. The BIST architecture utilizes the architectures and functions inherent to the bus and requires little extra hardware or dedicated interconnects between dies. Functionality and performance demos are verified and simulated under .13 μm technology. The energy cost estimate is 0.22 pJ/bit and maximum bandwidth per area is 1.42 Tb/mm2.}, booktitle={2013 ieee international 3d systems integration conference (3dic)}, author={Zhang, Z. Q. and Noia, B. and Chakrabarty, K. and Franzon, Paul}, year={2013} }
 @inproceedings{priyadarshi_choudhary_dwiel_upreti_rotenberg_davis_franzon_2013, title={Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors}, DOI={10.1109/isqed.2013.6523582}, abstractNote={Timing the transition of a processor design to a new technology poses a provocative tradeoff. On the one hand, transitioning as early as possible offers a significant competitive advantage, by bringing improved designs to market early. On the other hand, an aggressive strategy may prove to be unprofitable, due to the low manufacturing yield of a technology that has not had time to mature. We propose exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP). First, 3D integration facilitates a technology alloy. The CMP is split across two dies, one fabricated in the old technology and the other in the new technology. The alloy derives benefit from the new technology while limiting cost exposure. Second, to compensate for lower efficiency of old-technology cores, we exploit application and microarchitectural heterogeneity: applications which gain less from technology scaling are scheduled on old-technology cores, moreover, these cores are retuned to optimize this class of application. For a defect density ratio of 200 between 45nm and 65nm, Hetero2 3D gives 3.6× and 1.5× higher efficiency/cost compared to 2D and 3D homogeneous implementations, respectively, with only 6.5% degradation in efficiency. We also present a sensitivity analysis by sweeping the defect density ratio. The analysis reveals the defect density break-even points, where homogeneous 2D and 3D designs in 45nm achieve the same efficiency/cost as Hetero2 3D, marking significant points in the maturing of the technology.}, booktitle={Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013)}, author={Priyadarshi, S. and Choudhary, N. and Dwiel, B. and Upreti, A. and Rotenberg, E. and Davis, R. and Franzon, P.}, year={2013}, pages={1–7} }
 @inproceedings{sarkar_jayanti_spigna_lee_misra_franzon_2013, title={Investigation of intermediate dielectric for dual floating gate MOSFET}, DOI={10.1109/nvmts.2013.6851052}, abstractNote={A dual floating gate transistor offers potential as a unified memory, with simultaneous volatile and non-volatile storage. The quality of the dielectric between the two floating gates is critical to achieving the required dynamic cycle endurance. This paper reports on the results of early experiments into the material choice and process for this dielectric.}, booktitle={2013 13th Non-Volatile Memory Technology Symposium (NVMTS)}, author={Sarkar, B. and Jayanti, S. and Spigna, N. Di and Lee, B. and Misra, V. and Franzon, Paul}, year={2013} }
 @inproceedings{franzon_2013, title={MOOCs, OOCs, flips and hybrids: The new world of higher education}, DOI={10.1109/mse.2013.6566692}, abstractNote={A combination of new teaching methods, tools together with cloud services promises to deliver greater efficiency to higher education with improved teaching outcomes.}, booktitle={Proceedings ieee international conference on microelectronic systems}, author={Franzon, Paul}, year={2013}, pages={13–13} }
 @inproceedings{karim_franzon_kumar_2013, title={Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects}, DOI={10.1109/ectc.2013.6575674}, abstractNote={This paper compares the power efficiency of multiple 2D, 2.5D and 3D interconnect scenarios, specifically DDR3 with PCB, DDR3 with interposers, LPDDR2(3) with POP, wide I/Os with through-silicon vias (TSVs) and interposers and 32 nm technology CMOS drivers with TSVs and on-chip wires. It was found that DDR3 with PCB is the lowest power efficiency (15.65 mW/Gbps) and custom designed CMOS drivers optimized for the 2.5D and 3D give the highest power efficiency (0.23mW/Gbps). Optimization of a Back End of the Line (BEOL) 65 nm interposer interface is also presented for Wide IO interface to find maximize power efficiency. Power efficiency for different interposer trace lengths (5mm-40mm) and pitches (4.6μm-11.05μm) was analyzed. It was found that power efficiency decreases linearly with the increase of pitch and length of the interposer traces both in one stack and 4 stack die of Wide IO.}, booktitle={2013 IEEE 63rd Electronic Components and Technology Conference (ECTC)}, author={Karim, M. A. and Franzon, Paul and Kumar, A.}, year={2013}, pages={860–866} }
 @inproceedings{rotenberg_dwiel_forbes_zhang_widialaksono_chowdhury_tshibangu_lipa_davis_franzon_et al._2013, title={Rationale for a 3D heterogeneous multi-core processor}, ISBN={9781479929870}, url={http://dx.doi.org/10.1109/iccd.2013.6657038}, DOI={10.1109/iccd.2013.6657038}, abstractNote={Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient core type for that behavior.}, booktitle={2013 IEEE 31st International Conference on Computer Design (ICCD)}, publisher={IEEE}, author={Rotenberg, Eric and Dwiel, Brandon H. and Forbes, Elliott and Zhang, Zhenqian and Widialaksono, Randy and Chowdhury, Rangeen Basu Roy and Tshibangu, Nyunyi and Lipa, Steve and Davis, W. Rhett and Franzon, Paul and et al.}, year={2013}, month={Oct}, pages={154–168} }
 @inbook{di spigna_schinke_jayanti_misra_franzon_2013, title={Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates}, ISBN={9783642450723 9783642450730}, ISSN={1868-4238 1868-422X}, url={http://dx.doi.org/10.1007/978-3-642-45073-0_12}, DOI={10.1007/978-3-642-45073-0_12}, abstractNote={The operation of a novel unified memory device using two floating-gates is described through experimental characterization of a fabricated proof-of-concept device and confirmed through simulation. The dynamic, nonvolatile, and concurrent modes of the device are described in detail. Simulations show that the device compares favorably to conventional memory devices. Applications enabled by this unified memory device are discussed, highlighting the dramatic impact this device could have on next generation memory architectures.}, booktitle={VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design}, publisher={Springer Berlin Heidelberg}, author={Di Spigna, Neil and Schinke, Daniel and Jayanti, Srikant and Misra, Veena and Franzon, Paul}, year={2013}, pages={217–233} }
 @inproceedings{zhang_franzon_2013, title={TSV-based, modular and collision detectable face-to-back shared bus design}, DOI={10.1109/3dic.2013.6702399}, abstractNote={In this paper, we present a shared backbone bus solution specially tuned for modular 3DIC post-silicon-stacking. The proposed solution allows multiple parallel TSV-based channels to be placed and shared among various stacked components, which is uniquely supported by the dense connection pitch of the Face-to-back TSV bonding technology. To support the plug-n-play features, a distributed arbitration and collision detection structure is designed and evaluated. A demo of 16-channel shared bus is synthesized and verified under .13 μm technology. The conservative power estimate is 0.20 pJ/bit and bandwidth per area is 0.984 Tbps/mm2.}, booktitle={2013 ieee international 3d systems integration conference (3dic)}, author={Zhang, Z. Q. and Franzon, Paul}, year={2013} }
 @inproceedings{franzon_bar-cohen_2013, title={Thermal requirements in future 3D processors}, ISBN={9781467364843}, url={http://dx.doi.org/10.1109/3dic.2013.6702402}, DOI={10.1109/3dic.2013.6702402}, abstractNote={This paper reports on a study in which the projected thermal load of future 3D optimized embedded computers was explored. The approach taken was to project the performance, power consumption and area of a reasonably power-efficient 7 nm, 6672 core baseline conventionally packaged (“2D”) design, and 3D alternatives to this design. The 3D alternatives have improved power efficiency over the baseline 2D design, due to their reduced interconnect power consumptions and reduced processing overhead. The most efficient set of designs use more aggressive 3D-specific strategies to increase power efficiency at the expense of increased heat flux. The most efficient design is 38% more power efficient than the baseline 2D design, but has 13x the heat flux of that design. The value of that heat flux was 5.4 W/mm2. Further optimizations increase the thermal flux even further. Specifically creating architecture optimized to floating point operations, increases the heat flux to 17 W/mm2 while improving the computing efficiency by another 2x.}, booktitle={2013 IEEE International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Franzon, Paul and Bar-Cohen, Avi}, year={2013}, month={Oct} }
 @article{zhu_yelten_steer_franzon_2013, title={Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models}, volume={197}, ISBN={["978-3-642-34335-3"]}, ISSN={["2194-5365"]}, DOI={10.1007/978-3-642-34336-0_17}, abstractNote={This paper presents surrogate model-based methods to generate circuit performance models, device models, and high-speed IO buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. A new variation-aware IO buffer macromodel is developed by integrating surrogate modeling and a physically-based model structure. The new IO model provides both good accuracy and scalability for signal integrity analysis.}, journal={SIMULATION AND MODELING METHODOLOGIES, TECHNOLOGIES AND APPLICATIONS}, author={Zhu, Ting and Yelten, Mustafa Berke and Steer, Michael B. and Franzon, Paul D.}, year={2013}, pages={255–269} }
 @inproceedings{thorolfsson_lipa_franzon_2012, title={A 10.35 mW/GFlop Stacked SAR DSP unit using fine-grain partitioned 3D integration}, DOI={10.1109/cicc.2012.6330589}, abstractNote={In this paper we present a technique for implementing a fine-grain partitioned three-dimensional SAR DSP system using 3D placement of standard cells where only one of the 3D tiers is clocked to reduce clock power. We show how this technique was used to build the first fine-grain partitioned 3D integrated system to be demonstrated with silicon measurements in the literature, which is an ultra efficient floating-point synthetic aperture radar (SAR) DSP processing unit. The processing unit was fabricated in two tiers of GlobalFoundries, 1.5 V 130nm process that were 3D stacked face-to-face by Tezzaron. After fabrication the test chip was measured to consume 4.14 mW of power while running at 40 MHz operating for an operating efficiency of 10.35 mW/GFlop.}, booktitle={2012 ieee custom integrated circuits conference (cicc)}, author={Thorolfsson, T. and Lipa, S. and Franzon, Paul}, year={2012} }
 @article{harris_priyadarshi_melamed_ortega_manohar_dooley_kriplani_davis_franzon_steer_et al._2012, title={A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits}, volume={P}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2011.2178414}, abstractNote={A transient electrothermal simulation of a 3-D integrated circuit (3DIC) is reported that uses dynamic modeling of the thermal network and hierarchical electrothermal simulation. This is a practical alternative to full transistor electrothermal simulations that are computationally prohibitive. Simulations are compared to measurements for a token-generating asynchronous 3DIC clocking at a maximum frequency of 1 GHz. The electrical network is based on computationally efficient electrothermal macromodels of standard and custom cells. These are linked in a physically consistent manner with a detailed thermal network extracted from an OpenAccess layout file. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles.}, number={99}, journal={IEEE Trans CPMT}, author={Harris, T.R. and Priyadarshi, S. and Melamed, S. and Ortega, C. and Manohar, R. and Dooley, S.R. and Kriplani, N.M. and Davis, W.R. and Franzon, Paul and Steer, M.B. and et al.}, year={2012}, pages={1} }
 @article{chakraborti_toprakci_yang_di spigna_franzon_ghosh_2012, title={A compact dielectric elastomer tubular actuator for refreshable Braille displays}, volume={179}, ISSN={["0924-4247"]}, DOI={10.1016/j.sna.2012.02.004}, abstractNote={Electroactive polymer actuators stimulated by appropriate levels of electric field are particularly attractive for human-assist devices such as Braille. The development of a full page refreshable Braille display is very important for the integration of the visually impaired into the new era of communication. In this paper, development of a compact dielectric elastomer actuator suitable for Braille application is reported. The actuators are fabricated from commercially available silicone tubes. The tube has been rendered mechanically anisotropic through asymmetric levels of applied pretension in circumferential and axial directions in order to direct the actuation strain in the axial direction of the actuator. Key performance parameters, such as displacement, force, and response time of the actuator are investigated. The test results demonstrate the potential of the compact, lightweight, and low cost dielectric elastomer as actuators for a refreshable full page Braille display.}, journal={SENSORS AND ACTUATORS A-PHYSICAL}, author={Chakraborti, P. and Toprakci, H. A. Karahan and Yang, P. and Di Spigna, N. and Franzon, P. and Ghosh, T.}, year={2012}, month={Jun}, pages={151–157} }
 @inproceedings{di spigna_schinke_jayanti_misra_franzon_2012, title={A novel double floating-gate unified memory device}, ISBN={9781467326582}, url={http://dx.doi.org/10.1109/vlsi-soc.2012.7332076}, DOI={10.1109/vlsi-soc.2012.7332076}, abstractNote={A novel double floating-gate unified memory device is experimentally demonstrated for the first time. The device can be used to store both volatile and nonvolatile memory states simultaneously. Simulations of scaled devices show that the device offers several advantages compared to conventional memory devices. Such a device could have a dramatic impact on next generation memory architectures.}, booktitle={2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)}, publisher={IEEE}, author={Di Spigna, Neil and Schinke, Daniel and Jayanti, Srikant and Misra, Veena and Franzon, Paul}, year={2012}, month={Oct} }
 @inproceedings{ledford_gadfort_franzon_2012, title={An analysis of subthreshold SRAM bitcells for operation in low power RF-only technologies}, DOI={10.1109/subvt.2012.6404316}, abstractNote={Current RFID systems rely on the RF transciever to transmit information and convert RF power to DC to operate any integrated digital circuits. Research investigating the application of RF signals directly on digital CMOS circuits without RF-DC conversion is an emerging area for RFID technologies. One crucial digital circuit for most RFID systems is memory, needed for storing operational instructions and sampled data. An in-depth study and comparison of subthreshold SRAM bitcells has been conducted to analyze how such memories will function in a subthreshold RF-only regime without the need for RF-DC conversion. Several SRAM cells were chosen for conversion into the RF-only family and measured against several metrics, including highest performance at lowest operating voltage, power consumption, and static noise margins (SNM). Including RF supply transistors, an 18-T subthreshold RF-only bitcell is proposed, capable of operating at a data rate of 100 kHz at VRF of 200mVRMS.}, booktitle={2012 IEEE subthreshold microelectronics conference (SUBVT)}, author={Ledford, J. and Gadfort, P. and Franzon, Paul}, year={2012} }
 @article{yelten_franzon_steer_2012, title={Analog Negative-Bias-Temperature-Instability Monitoring Circuit}, volume={12}, ISSN={["1558-2574"]}, DOI={10.1109/tdmr.2011.2178096}, abstractNote={A negative-bias-temperature-instability (NBTI) monitor subcircuit is presented and implemented in 65-nm CMOS technology. The subcircuit can be incorporated in various analog circuit blocks subject to different variability, stress, and aging histories. For an amplifier block, the NBTI monitor is a linear sensor, and sensing is provided as variation of the amplifier gain in response to NBTI-induced bias variation. The monitor sensitivity in this configuration is 3.15 V-1 and is demonstrated through electrothermal stress on the amplifier circuit.}, number={1}, journal={IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY}, author={Yelten, Mustafa Berke and Franzon, Paul D. and Steer, Michael B.}, year={2012}, month={Mar}, pages={177–179} }
 @article{lou_yan_zhang_franzon_2012, title={Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods}, volume={28}, ISSN={["1573-0727"]}, DOI={10.1007/s10836-011-5261-4}, number={1}, journal={JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS}, author={Lou, Yi and Yan, Zhuo and Zhang, Fan and Franzon, Paul D.}, year={2012}, month={Feb}, pages={27–38} }
 @inproceedings{charles_franzon_2012, title={Comparison of TSV-based PDN-design effects using various stacking topology methods}, DOI={10.1109/epeps.2012.6457848}, abstractNote={In this study, we estimate, compare and analyze the PDN effects of four chip-stacking topologies. The chip-stacking topologies are: (1) F2B; (2) F2F; (3) B2F; and (4) B2B. The arrangement of various on-chip interconnect elements based on the chip-stacking topologies specific to the design of 3D IC-PDN, varies in impedance properties. To reduce the impedance effects NMOS decap unit cells are integrated into PDN system to suppress 3D-SSN. Conclusively, the results of the case study indicate B2F and F2B die stacking topologies results in lower impedance effects relative to F2F topology.}, booktitle={Ieee conference on electrical performance of electronic packaging and}, author={Charles, G. and Franzon, Paul}, year={2012}, pages={83–86} }
 @article{yelten_franzon_steer_2012, title={Comparison of modeling techniques in circuit variability analysis}, volume={25}, ISSN={["1099-1204"]}, DOI={10.1002/jnm.836}, abstractNote={SUMMARY}, number={3}, journal={INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS}, author={Yelten, Mustafa Berke and Franzon, Paul D. and Steer, Michael B.}, year={2012}, pages={288–302} }
 @inproceedings{franzon_davis_zhou_priyadarshi_hogan_karnik_srinavas_2012, title={Coordinating 3D designs: Interface IP, standards or free form?}, ISBN={9781467321907 9781467321891 9781467321884}, url={http://dx.doi.org/10.1109/3dic.2012.6262960}, DOI={10.1109/3dic.2012.6262960}, abstractNote={Three dimensional integration technology introduces new complexities to design and particularly codesign. Additional complexity is added when one considers that the design needs to be “future-proof”. How do you ensure that the 3D chip stack will work for future chips within the stack, whose parameters are yet to be fully anticipated. This paper proposes that this be managed through an Interface IP approach Design blocks with associated properties that not only supports signaling and power delivery but also constraints that must be managed between chips both during design but also in-situ and as part of physical verification.}, booktitle={2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International}, publisher={IEEE}, author={Franzon, P. D. and Davis, W. R. and Zhou, Zheng and Priyadarshi, S. and Hogan, M. and Karnik, T. and Srinavas, G.}, year={2012}, month={Jan} }
 @article{yelten_zhu_koziel_franzon_steer_2012, title={Demystifying Surrogate Modeling for Circuits and Systems}, volume={12}, ISSN={1531-636X}, url={http://dx.doi.org/10.1109/mcas.2011.2181095}, DOI={10.1109/mcas.2011.2181095}, abstractNote={In this article, grey-box and black-box surrogate modeling are described, with some key findings. The important point is that surrogate modeling has a solid mathematical basis leading to what has become a dramatic increase in our ability to develop engineering models and to engineer systems. In Section 2, a systematic approach to constructing surrogate models is provided. Each step is explained using published methods. Section 3 presents surrogate modeling examples from the domain of circuits and systems.}, number={1}, journal={IEEE Circuits and Systems Magazine}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Yelten, M. B. and Zhu, Ting and Koziel, S. and Franzon, P. D. and Steer, M. B.}, year={2012}, pages={45–63} }
 @inproceedings{gadfort_franzon_2012, title={Design, modeling, and fabrication of mm(3) three-dimensional integrated antennas}, DOI={10.1109/ectc.2012.6249081}, abstractNote={This paper describes the design, modeling, and fabrication methods of a new method to build three-dimensional integrated antenna arrays. The goal is to create a mm-scale sensor for implantation in the human body. Since the orientation of the sensor is not known in advance the antenna must work equally well in all directions. The best way to do this is to build antennas on each side of a cubic structure. The antenna is intended for near field power harvesting. By utilizing the edge antenna the power transfer efficiency can be increased by 18.9 dB at even the worst orientations for the sensors. Another application would be to create an omnidirectional antenna for high frequency mobile devices.}, booktitle={2012 IEEE 62nd Electronic Components and Technology Conference (ECTC)}, author={Gadfort, P. and Franzon, Paul}, year={2012}, pages={1794–1799} }
 @article{priyadarshi_harris_melamed_otero_kriplani_christoffersen_manohar_dooley_davis_franzon_et al._2012, title={Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels}, volume={6}, ISSN={1751-858X}, url={http://dx.doi.org/10.1049/iet-cds.2011.0061}, DOI={10.1049/iet-cds.2011.0061}, abstractNote={Physics-based compact electrothermal macromodels of standard cells are developed for fast dynamic simulation of three-dimensional integrated circuits (3DICs). Such circuits can have high thermal densities and thermal effects often limit their performance. The macromodels developed here use fewer state-variables than a discrete transistor-level implementation while retaining transistor-level accuracy. This results in significant speed-up over transistor-level simulation for large-scale circuits. The macromodel-based methodology enables robust and significantly faster dynamic electrothermal simulation over the long times required for thermal transients to subside. Consequently, transient junction temperature can be examined in the design phase. Simulated junction and measured surface thermal transients are compared.}, number={1}, journal={IET Circuits, Devices & Systems}, publisher={Institution of Engineering and Technology (IET)}, author={Priyadarshi, S. and Harris, T.R. and Melamed, S. and Otero, C. and Kriplani, N.M. and Christoffersen, C.E. and Manohar, R. and Dooley, S.R. and Davis, W.R. and Franzon, P.D. and et al.}, year={2012}, pages={35} }
 @article{melamed_thorolfsson_harris_priyadarshi_franzon_steer_davis_2012, title={Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring}, volume={31}, DOI={10.1109/tcad.2011.2180384}, abstractNote={The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity “far response” in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.}, number={5}, journal={IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems}, author={Melamed, S. and Thorolfsson, T. and Harris, T. R. and Priyadarshi, S. and Franzon, Paul and Steer, M. B. and Davis, W. R.}, year={2012}, pages={676–689} }
 @inproceedings{gadfort_franzon_2012, title={Near threshold RF-only analog to digital converter}, DOI={10.1109/subvt.2012.6404321}, abstractNote={This paper describes an analog-to-digital converter (ADC) capable of operating in a RF-only circuit topology. A major limitation to direct RF-powered sensors are the lack of analog circuits. The proposed architecture is comprised of a cross-coupled pair of inverters, which act as the comparator for the ADC. This setup has been simulated in IBMs 0.13 μm bulk CMOS process for a 3 bit analog-to-digital converter (ADC). At a RF supply voltage of 300 mVRMS and frequency 13.57 MHz, the ADC has a resolution of 20 mV and can resolve voltages ranging from -80 mV to 80 mV, and at a frequency of 915 MHz the ADC can resolve voltages ranging from -140 mV to 140 mV. In order to optimize the ADC operation, the sampling time has been adjusted to one-third of the evaluation time, to give the comparator enough time to complete the amplification.}, booktitle={2012 IEEE subthreshold microelectronics conference (SUBVT)}, author={Gadfort, P. and Franzon, Paul}, year={2012} }
 @article{priyadarshi_saunders_kriplani_demircioglu_davis_franzon_steer_2012, title={Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning}, volume={31}, ISSN={["1937-4151"]}, DOI={10.1109/tcad.2012.2201156}, abstractNote={A parallel transient simulation technique for multiphysics circuits is presented. The technique develops partitions utilizing the inherent delay present within a circuit and between physical domains. A state-variable-based circuit delay element is presented, which implements the coupling between two spatially or temporally isolated circuit partitions. A parallel delay-based iterative approach for interfacing delay-partitioned subcircuits is applied, which achieves the reasonable accuracy of nonparallel circuit simulation if both incorporate the same interblock delay. The partitioned subcircuits are distributed to different cores of a shared-memory multicore processor and solved in parallel. A multithreaded implementation of the methodology using OpenMP is presented. Examples showing superlinear speedup compared to unpartitioned single-core simulation using the direct method are presented. This paper also discusses the impact of load balancing and absolute delay on simulation speedup.}, number={10}, journal={IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS}, author={Priyadarshi, Shivam and Saunders, Christopher S. and Kriplani, Nikhil M. and Demircioglu, Harun and Davis, W. Rhett and Franzon, Paul D. and Steer, Michael B.}, year={2012}, month={Oct}, pages={1522–1535} }
 @inproceedings{priyadarshi_hu_choi_melamed_chen_davis_franzon_2012, title={Pathfinder 3D: A flow for system-level design space exploration}, ISBN={9781467321907 9781467321891 9781467321884}, url={http://dx.doi.org/10.1109/3dic.2012.6262961}, DOI={10.1109/3dic.2012.6262961}, abstractNote={Three dimensional integration technology has the potential to provide enhanced performance and device density gains beyond that available from technology scaling alone. However, it provides plethora of design choices for system designers. The full exploitation of the benefits of 3D integration requires a system-level exploration flow which can facilitate in finding an optimal 3D design by comparing possible early design choices. In this paper we present a flow for fast system-level exploration useful for path finding studies. The flow enables users to explore the tradeoff between different stacking and partitioning schemes in terms of performance, power, and temperature. We also present a free open source design kit compiler, FreePDK3D45 and a tool for fast floorplan evaluation of TSV-based digital architectures, Pathfinder3D. The open source design kit and architecture evaluator can help the community to research, learn and explore the various aspects of 3D integration. Using the proposed flow and design kit, we present a case study of 3D integration of a Network on Chip. This case study demonstrates system-level comparisons of the performance, power and temperature of different homogenously partitioned stacking schemes.}, booktitle={2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International}, publisher={IEEE}, author={Priyadarshi, S. and Hu, J. and Choi, W.H. and Melamed, S. and Chen, X. and Davis, W.R. and Franzon, P.D.}, year={2012}, month={Jan} }
 @inproceedings{yelten_franzon_steer_2012, title={Process mismatch analysis based on reduced-order models}, DOI={10.1109/isqed.2012.6187561}, abstractNote={This paper describes a methodology based on reduced-order models to investigate the effects of process mismatch in analog circuits in the presence of reliability degradation. Neural network-based reduced-order models for the DC drain current, Ids, of 65 nm n- and p-channel transistors have been generated in terms of six process parameters, temperature, and device age. The models identify the contribution of process parameters to the mismatch of n- and p-channel transistors as they age. Hot carrier injection (HCI) is considered as the main reliability degradation for n-channel devices and negative bias temperature instability (NBTI) is considered for p-channel devices. It is demonstrated that the variations of the effective channel length and intrinsic threshold voltage are major contributors to device mismatch in the absence of aging. Finally, a beta multiplier current reference is analyzed using the developed models for the impact of process mismatch with and without the aging effects. It is shown that in a cascode current mirror the variability of the reference current can be reduced by ensuring that the same rail transistors experience similar variations.}, booktitle={2012 13th international symposium on quality electronic design (isqed)}, author={Yelten, M. B. and Franzon, Paul and Steer, M. B.}, year={2012}, pages={648–655} }
 @inproceedings{yan_won_franzon_aygun_braunisch_2012, title={S-parameter based multimode signaling}, DOI={10.1109/epeps.2012.6457832}, abstractNote={As the demands for higher density of interconnects and denser packages are increasing, crosstalk is becoming more important in input/output (I/O) design. Multimode signaling has been investigated for crosstalk cancellation. This paper presents a new scattering parameter (S-parameter) based methodology for multimode signaling. The set of coder/decoder coefficients (CODEC) is obtained from the S-parameters of the whole channel, which makes the scheme more applicable for practical systems. The derived CODEC shows a 20 dB improvement in signal-to-noise ratio and 45% reduction of root mean square (RMS) jitter compared with single-ended signaling for a practical benchmark problem.}, booktitle={Ieee conference on electrical performance of electronic packaging and}, author={Yan, Z. and Won, C. Y. and Franzon, Paul and Aygun, K. and Braunisch, H.}, year={2012}, pages={11–14} }
 @article{zhu_steer_franzon_2012, title={Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits}, volume={29}, ISSN={0740-7475}, DOI={10.1109/mdt.2012.2220332}, abstractNote={Analog circuits designed in submicrometer nodes suffer from process variations, typically requiring calibration in order to center their performance parameters and to recover yield loss. This article presents a design flow to find appropriate tuning knob settings to compensate for different process variation scenarios.}, number={6}, journal={IEEE Design Test of Computers}, author={Zhu, T. and Steer, M. B. and Franzon, P. D.}, year={2012}, month={Dec}, pages={74–83} }
 @inproceedings{franzon_davis_thorolfsson_melamed_2011, title={3D specific systems design and CAD}, ISBN={9781457708022}, url={http://dx.doi.org/10.1109/samos.2011.6045479}, DOI={10.1109/samos.2011.6045479}, abstractNote={3D stacking and integration can provide significant system advantages. Following a brief technology review, this abstract explores application drivers, design and CAD for 3D ICs. The main 3D exploitation explored in detail is that of logic on memory. This application is explored in a specific DSP example, showing a 25% power advantage when implemented in 3D compared with 2D. Finally critical areas that need better solutions are explored. These include cost management, design planning, test management, and thermal management.}, booktitle={2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation}, publisher={IEEE}, author={Franzon, Paul D. and Davis, W. Rhett and Thorolfsson, Thor and Melamed, Samson}, year={2011}, month={Jul} }
 @inproceedings{franzon_davis_thorolfsson_melamed_2011, title={3D specific systems: Design and CAD}, DOI={10.1109/ats.2011.99}, abstractNote={3D stacking and integration can provide significant system advantages. Following a brief technology review, this abstract explores application drivers, design and CAD for 3D ICs. The main 3D exploitation explored in detail is that of logic on memory. This application is explored in a specific DSP example, showing a 25% power advantage when implemented in 3D compared with 2D. Finally critical areas that need better solutions are explored. These include cost management, design planning, test management, and thermal management.}, booktitle={2011 Asian Test Symposium}, author={Franzon, P. D. and Davis, W. R. and Thorolfsson, T. and Melamed, S.}, year={2011}, pages={470–473} }
 @article{zhu_steer_franzon_2011, title={Accurate and Scalable IO Buffer Macromodel Based on Surrogate Modeling}, volume={1}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2011.2138704}, abstractNote={In this paper, a new method is proposed to generate accurate and scalable macromodels for input/output buffers. The method characterizes the physically based model elements with adaptive multivariate surrogate modeling techniques in order to achieve high fidelity and process–voltage–temperature scalability. Both single-ended and differential output buffer circuit examples demonstrate that the proposed modeling method offers good accuracy and flexible scalability to facilitate signal integrity analysis.}, number={8}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Zhu, Ting and Steer, Michael B. and Franzon, Paul D.}, year={2011}, month={Aug}, pages={1240–1249} }
 @inproceedings{chen_davis_franzon_2011, title={Adaptive clock distribution for 3D integrated circuits}, DOI={10.1109/epeps.2011.6100195}, abstractNote={Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many challenges. In this work, we present new techniques for realizing highly adaptive and reliable clock distribution for 3D ICs. Firstly, an efficient clock distribution topology without need of balanced H-tree is proposed. Secondly, a robust tunable-delay-buffer (TDB) circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry. Moreover, a design optimization flow is constructed for improving the adaptive clock design based on the thermal profiles. Experiment results show that the clock skews are significantly reduced using the proposed techniques.}, booktitle={2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems}, author={Chen, X. and Davis, W. R. and Franzon, P. D.}, year={2011}, pages={91–94} }
 @inproceedings{charles_franzon_kim_levin_2011, title={Analysis and approach of TSV-based hierarchical power distribution networks for estimating 1st-droop and resonant noise in 3DIC}, DOI={10.1109/epeps.2011.6100243}, abstractNote={In this paper, we model and analyse a hierarchical TSV-based chip-package co-design of the power delivery network (PDN) for three-dimensional integrated circuits (3DICs). It is a significant design consideration to combine chip/package PDN structures, accurately characterize and quantify their overall impedance, 1st-droop effect and resonant noise behaviour for multi-stacked chips. To better understand how to reduce noise, particularly simultaneous switching noise (SSN) and determine voltage drop impact on power delivery networks for 3DICs, an analytical model is enhanced and applied to estimate the different noise levels of hierarchical TSV-based PDN structures. The on-chip parasitic capacitances and intentionally added decoupling capacitors help counter any Ldi/dt variations from the power supply rails as a result of the inductive effects in TSVs. With technology interest in embedded applications, the hierarchical chip-package TSV-based PDN design is modeled after a multi-stacked memory subsystem, a silicon interposer and package structure. A segmentation-based method is used to calculate the overall impedance of the hierarchical PDN system. An analytical expression is modified and used to quantify the transient response characteristics of 1st-droop and resonant noise property.}, booktitle={Ieee conference on electrical performance of electronic packaging and}, author={Charles, G. and Franzon, Paul and Kim, J. and Levin, A.}, year={2011}, pages={267–270} }
 @article{schinke_di spigna_shiveshwarkar_franzon_2011, title={Computing with Novel Floating-Gate Devices}, volume={44}, ISSN={["1558-0814"]}, DOI={10.1109/mc.2010.366}, abstractNote={The authors report on the design, operation, and architectural implications of single and double floating-gate devices for nontraditional applications enabling low-power FPGAs and analog-to-digital converters, and propose a unified nonvolatile/volatile memory device.}, number={2}, journal={COMPUTER}, author={Schinke, Daniel and Di Spigna, Neil and Shiveshwarkar, Mihir and Franzon, Paul}, year={2011}, month={Feb}, pages={29–36} }
 @inproceedings{franzon_liu_2011, title={Design strategies for processor, chip/package co-design (M-VI)}, ISBN={9781424494019 9781424493982 9781424494002}, url={http://dx.doi.org/10.1109/epeps.2011.6100173}, DOI={10.1109/epeps.2011.6100173}, abstractNote={Start of the above-titled section of the conference proceedings record.}, booktitle={2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems}, publisher={IEEE}, author={Franzon, Paul and Liu, En-Xiao}, year={2011}, month={Oct} }
 @article{thorolfsson_moezzi-madani_franzon_2011, title={Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor}, volume={5}, ISSN={["1751-861X"]}, DOI={10.1049/iet-cdt.2009.0106}, abstractNote={In this study, the authors present a floating-point synthetic aperture radar processor that achieves a power efficiency of 18.0 mW/GFlop in simulation through the use of three-dimensional (3D) integration and reconfiguration of the data path. The reconfiguration reduces the number of arithmetic units required in every processing element (PE) from 24 down to 10. The processor uses a 3D integrated memory that reduces the memory power consumption by 70% when compared to a 2D memory. The system processes a SAR image using a two-tier 3D integrated PE, which when compared to an equivalent 2D PE decreases the power consumed in the interconnect of each PE by 15.5% and the footprint by 49.2%, and allows the PE to operate 7.1% faster in simulation. Additionally, by using 3D integration in the memory one can reduce the power consumption of the memory by 70%. Furthermore, the authors show how the 3D aspects of the processor can be realised by using 2D tools, when used in conjunction with the proposed through-silicon via assignment algorithm.}, number={3}, journal={IET COMPUTERS AND DIGITAL TECHNIQUES}, author={Thorolfsson, T. and Moezzi-Madani, N. and Franzon, P. D.}, year={2011}, month={May}, pages={198–204} }
 @article{schinke_priyadarshi_pitts_di spigna_franzon_2011, title={SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation}, volume={5}, ISSN={["1751-858X"]}, DOI={10.1049/iet-cds.2010.0410}, abstractNote={The majority of nanocrystal floating gate research has been done at the device level. Circuit-level research is still in its early stages because of the lack of a physical device model appropriate for circuit simulations. In this study, a comprehensive and accurate SPICE-compatible physical equation-based model of nanocrystal floating gate devices is developed based on uniform direct tunnelling and Fowler-Nordheim tunnelling. The main contribution is a Verilog-A module that captures the physical behaviours of programming and erasing the device. A predictive NMOS model is then used for modelling the conduction channel to determine the behavioural I - V characteristics. The proposed model uses only explicit formulae resulting in fast computation appropriate for circuit simulation and can be used in any SPICE simulator supporting Verilog-A. It interacts dynamically with the rest of the circuit and includes charge leakage which enables power consumption analysis. The simulation results of the proposed model fit well to experimental results of various fabricated devices. Additionally, it is verified in HSPICE, demonstrating a significant speedup and good agreement with a numerical device simulator. This study is important in bridging the gap between device- and circuit-level research.}, number={6}, journal={IET CIRCUITS DEVICES & SYSTEMS}, author={Schinke, D. and Priyadarshi, S. and Pitts, W. Shepherd and Di Spigna, N. and Franzon, P.}, year={2011}, month={Nov}, pages={477–483} }
 @article{yelten_franzon_steer_2011, title={Surrogate Model-Based Analysis of Analog Circuits – Part I. Variability Analysis}, volume={PP}, number={99}, journal={IEEE Transactions on Device and Materials Reliability}, author={Yelten, M.B. and Franzon, P.D. and Steer, M.B.}, year={2011} }
 @inproceedings{su_pitts_franzon_wilson_2010, title={A zero power consumption Multi-Capacitor structure for voltage summing in high-speed FFE}, ISBN={9781424468652}, url={http://dx.doi.org/10.1109/epeps.2010.5642532}, DOI={10.1109/epeps.2010.5642532}, abstractNote={Conventional current-mode summation utilized in feed-forward equalization (FFE) has disadvantages in power consumption and linearity and thus becomes less attractive when high-speed low-power equalization is required. A Multi-Capacitor (MultiCap) structure is presented to overcome these disadvantages by supporting voltage-mode summation. This passive structure replaces the current-summation block of the transmit FFE and has zero power consumption. A set of equations are derived to estimate the useable value of the MultiCap, of which the range is bounded by I/O pitch, receiver sensitivity, and other parameters. The parasitics of this device are proven to be negligible. Simulation in 0.13µm standard CMOS process shows that the MultiCap structure could enable a power saving of more than 90% over the conventional current-mode FFE.}, booktitle={19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems}, publisher={IEEE}, author={Su, Bruce and Pitts, W. Shepherd and Franzon, Paul D. and Wilson, John}, year={2010}, month={Oct} }
 @inproceedings{franzon_davis_thorolffson_2010, title={Creating 3D specific systems: Architecture, design and CAD}, ISBN={9783981080162 9781424470549 9783981080162}, url={http://dx.doi.org/10.1109/date.2010.5457086}, DOI={10.1109/date.2010.5457086}, abstractNote={3D stacking and integration can provide system advantages. Following a brief technology review, this abstract explores application drivers, design and CAD for 3D ICs. The main application area explored in detail is that of logic on memory. This application is explored in a specific DSP example. Finally critical areas that need better solutions are explored. These include design planning, test management, and thermal management.}, booktitle={2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)}, publisher={IEEE}, author={Franzon, Paul D and Davis, W Rhett and Thorolffson, Thor}, year={2010}, month={Mar}, pages={1684–1688} }
 @inproceedings{thorolfsson_luo_cong_franzon_2010, title={Logic-on-logic 3D integration and placement}, ISBN={9781457705267}, url={http://dx.doi.org/10.1109/3dic.2010.5751451}, DOI={10.1109/3dic.2010.5751451}, abstractNote={In this paper we describe three 3D standard cell placement algorithms, which are: “3D Placement using Sequential Off-the-Shelf 2D Placement Tools”, “True-3D Analytical Placement with mPL” and “3D Placement using Simultaneous 2D Placements with mPL”. We use these algorithms to place three case studies in a real face-to-face 3D integration process. The three case studies are a 2 point FFT butterfly processing element (PE), an Advanced Encryption Standard encryption block (AES) and a multiple-input and multiple-output wireless decoder (MIMO). The placements are then fully routed and compared to 2D placements in terms of performance and power consumption. Using this methodology we show that using 3D face-to-face integration with microbumps in conjunction with the three placement algorithms we can improve the maximum clock speed of AES module by 15.3% and the PE by 22.6%, while reducing the power of the AES module and the PE by 2.6% and 12.9% respectively.}, booktitle={2010 IEEE International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Thorolfsson, Thorlindur and Luo, Guojie and Cong, Jason and Franzon, Paul D.}, year={2010}, month={Nov} }
 @article{choi_braunisch_ayguen_franzon_2010, title={Multimode Transceiver for High-Density Interconnects: Measurement and Validation}, ISSN={["2377-5726"]}, DOI={10.1109/ectc.2010.5490738}, abstractNote={The demand for high-density links is increasing as the trend towards more cost-effective and high-throughput systems continues. Whereas the conventional single-ended and differential signaling schemes need a guaranteed interpair spacing which imposes certain bounds on maximum achievable signaling density, multimode signaling can be utilized to further increase it. In this paper, first, the exacerbated crosstalk caused by highly-coupled lines is illustrated to demonstrate the motivation for multimode signaling. A multimode signaling transceiver is then designed to prove the concept of multimode signaling. The measurement results of the decoded receiver output demonstrate that this scheme is able to reduce the effective crosstalk in a multi-wire link.}, journal={2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)}, author={Choi, Yongjin and Braunisch, Henning and Ayguen, Kemal and Franzon, Paul D.}, year={2010}, pages={1733–1738} }
 @inproceedings{lipa_thorolfsson_franzon_2010, title={The NCSU Tezzaron design kit}, ISBN={9781457705267}, url={http://dx.doi.org/10.1109/3dic.2010.5751418}, DOI={10.1109/3dic.2010.5751418}, abstractNote={A collection of slides from the authors' conference is given. Topics include NCSU design kit user guide, Verilog memory model, and lessons learned in assembling the reticle.}, booktitle={2010 IEEE International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Lipa, S. and Thorolfsson, T. and Franzon, P.}, year={2010}, pages={1–15} }
 @article{di spigna_chakraborti_winick_yang_ghosh_franzon_2010, title={The integration of novel EAP-based Braille cells for use in a refreshable tactile display}, volume={7642}, ISSN={["1996-756X"]}, DOI={10.1117/12.847666}, abstractNote={Structures demonstrating the viability of both the hydraulic and latching Braille dot, and the dielectric elastomer fiber Braille dot have been fabricated and characterized. A hydraulic proof-of-concept structure has achieved the necessary volumetric change required to lift a Braille dot over 0.5mm at voltages under 1000V and at speeds under 100ms. Long bimorphs have been fabricated that demonstrate large tip displacements over 2mm that could be used to mechanically latch the Braille rod in the 'up' position to achieve the force requirement. The addition of radial prestrain in dielectric elastomer tubes has reduced the wall thickness and directed the strain in the axial direction which has had a dramatic impact on their resulting characteristics. The required bias voltage for the dielectric elastomer fiber Braille dot has been reduced from 15.5kV to 8.75kV while the Braille head tip displacement of a fabricated prototype has almost tripled on average and now also exceeds the required displacement for a refreshable Braille display. Finally, potential solutions to the current shortcomings of both designs in meeting all of the requirements for such a display are discussed.}, journal={ELECTROACTIVE POLYMER ACTUATORS AND DEVICES (EAPAD) 2010}, author={Di Spigna, N. and Chakraborti, P. and Winick, D. and Yang, P. and Ghosh, T. and Franzon, P.}, year={2010} }
 @inproceedings{melamed_thorolfsson_srinivasan_cheng_franozn_davis_2010, title={Thermal Investigatoin of Tier Swapping to Improve the Thermal Profile of Memory-on-Logic 3DICs}, booktitle={IEEE THERMINIC}, author={Melamed, S. and Thorolfsson, T. and Srinivasan, A. and Cheng, E. and Franozn, P. and Davis, W.}, year={2010}, pages={1–6} }
 @inproceedings{franzon_wilson_li_2010, title={Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications}, ISBN={9781457705267 9781457705274}, url={http://dx.doi.org/10.1109/3dic.2010.5751431}, DOI={10.1109/3dic.2010.5751431}, abstractNote={In a 3D chip stack, it is important to thermally isolate any DRAMs from high power processors, so that the former can operate at low junction temperatures. One way to do this is to use the combination of a vacuum gap, formed using standard semiconductor processing, together with capacitive or inductive signaling across the gap. Simulation shows that the DRAM can operate at a temperature 47°C cooler than the CPU.}, booktitle={2010 IEEE International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Franzon, Paul and Wilson, John and Li, Ming}, year={2010}, month={Nov} }
 @article{zhang_wilson_bashirullah_luo_xu_franzon_2009, title={A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling}, volume={17}, ISSN={1063-8210 1557-9999}, url={http://dx.doi.org/10.1109/tvlsi.2008.2002682}, DOI={10.1109/TVLSI.2008.2002682}, abstractNote={This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.}, number={9}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Zhang, Liang and Wilson, John M. and Bashirullah, Rizwan and Luo, Lei and Xu, Jian and Franzon, Paul D.}, year={2009}, month={Sep}, pages={1267–1274} }
 @inproceedings{thorolfsson_moezzi-madani_franzon_2009, title={A low power 3D integrated FFT engine using hypercube memory division}, DOI={10.1145/1594233.1594289}, abstractNote={In this paper we demonstrate a floating point FFT processor that leverages both 3D integration and a hypercube memory division scheme to reduce the power consumption of a 1024 point FFT down to 4.227 μJ. The hypercube memory division scheme lowers the energy per memory access by 59.2% while only increasing the total area required by 16.8%, while using 3D integration reduces the logic power by 5.2%. For comparison, we analyze the amount of power and wire length reduction that can be expected from 3D integration for normal digital logic circuits.}, booktitle={ISLPED 09}, author={Thorolfsson, T. and Moezzi-Madani, N. and Franzon, Paul}, year={2009}, pages={231–236} }
 @inproceedings{zhu_franzon_2009, title={An enhanced macromodeling approach for differential output drivers}, DOI={10.1109/bmas.2009.5338889}, abstractNote={This paper presents an approach for building new compact macromodels of differential output drivers. Composed of enhanced physical-based elements, the new models are capable of capturing the important intrinsic nonlinear and dynamic characteristics of the drivers. We demonstrate the approach with two typical digital drivers, low-voltage differential signaling (LVDS) driver and pre-emphasis driver. The obtained macromodels achieve excellent accuracy in capturing behaviors at various input patterns, loading conditions and supply voltages.}, booktitle={BMAS 2009: Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop}, author={Zhu, T. and Franzon, Paul}, year={2009}, pages={54–59} }
 @article{davis_oh_sule_franzon_2009, title={Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies}, volume={17}, ISSN={["1557-9999"]}, DOI={10.1109/TVLSI.2008.2009352}, abstractNote={3-D stacking and integration can provide system advantages. This paper explores application drivers and computer-aided design (CAD) for 3-D integrated circuits (ICs). Interconnect-rich applications especially benefit, sometimes up to the equivalent of two technology nodes. This paper presents physical-design case studies of ternary content-addressable memories (TCAMs), first-in first-out (FIFO) memories, and a 8192-point fast Fourier transform (FFT) processor in order to quantify the benefit of the through-silicon vias in an available 180-nm 3-D process. The TCAM shows a 23% power reduction and the FFT shows a 22% reduction in cycle-time, coupled with an 18% reduction in energy per transform.}, number={4}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Davis, W. Rhett and Oh, Eun Chu and Sule, Ambarish M. and Franzon, Paul D.}, year={2009}, month={Apr}, pages={496–506} }
 @inproceedings{di spigna_chakraborti_yang_ghosh_franzon_2009, title={Application of EAP materials toward a refreshable Braille display}, url={http://dx.doi.org/10.1117/12.816009}, DOI={10.1117/12.816009}, abstractNote={The development of a multiline, refreshable Braille display will assist with the full inclusion and integration of blind people into society. The use of both polyvinylidene fluoride (PVDF) film planar bending mode actuators and silicone dielectric elastomer cylindrical tube actuators have been investigated for their potential use in a Braille cell. A liftoff process that allows for aggressive scaling of miniature bimorph actuators has been developed using standard semiconductor lithography techniques. The PVDF bimorphs have been demonstrated to provide enough displacement to raise a Braille dot using biases less than 1000V and operating at 10Hz. In addition, silicone tube actuators have also been demonstrated to achieve the necessary displacement, though requiring higher voltages. The choice of electrodes and prestrain conditions aimed at maximizing axial strain in tube actuators are discussed. Characterization techniques measuring actuation displacement and blocking forces appropriate for standard Braille cell specifications are presented. Finally, the integration of these materials into novel cell designs and the fabrication of a prototype Braille cell are discussed.}, booktitle={Electroactive Polymer Actuators and Devices (EAPAD) 2009}, publisher={SPIE}, author={Di Spigna, N. and Chakraborti, P. and Yang, P. and Ghosh, T. and Franzon, P.}, editor={Bar-Cohen, Yoseph and Wallmersperger, ThomasEditors}, year={2009}, month={Mar} }
 @inproceedings{zhu_franzon_2009, title={Application of surrogate modeling to generate compact and PVT-sensitive IBIS models}, DOI={10.1109/epeps.2009.5338472}, abstractNote={A new proposal of applying surrogate-modeling in Input-output Buffer Information Specification (IBIS) is presented. It saves the IBIS data storage resource, extends the model utility to various process-voltage-temperature (PVT) simulations and eliminates the data interpolation deviations.}, booktitle={Electrical Performance of Electronic Packaging and Systems}, author={Zhu, T. and Franzon, Paul}, year={2009}, pages={77–80} }
 @inproceedings{franzon_davis_steer_thorolfsson_mcilrath_obermiller_2009, title={CAD and Design Application Exploration of 3DICs}, booktitle={Proceedings 2008 Gomactech}, author={Franzon, P. and Davis, W. and Steer, M. and Thorolfsson, T. and McIlrath, L. and Obermiller, K.}, year={2009}, month={Apr} }
 @article{he_corley_lu_di spigna_he_nackashi_franzon_tour_2009, title={Controllable Molecular Modulation of Conductivity in Silicon-Based Devices}, volume={131}, ISSN={["0002-7863"]}, DOI={10.1021/ja9002537}, abstractNote={The electronic properties of silicon, such as the conductivity, are largely dependent on the density of the mobile charge carriers, which can be tuned by gating and impurity doping. When the device size scales down to the nanoscale, routine doping becomes problematic due to inhomogeneities. Here we report that a molecular monolayer, covalently grafted atop a silicon channel, can play a role similar to gating and impurity doping. Charge transfer occurs between the silicon and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. The partly charged end-groups of the grafted molecular layer may act as a top gate. The doping- and gating-like effects together lead to the observed controllable modulation of conductivity in pseudometal-oxide-semiconductor field-effect transistors (pseudo-MOSFETs). The molecular effects can even penetrate through a 4.92-mum thick silicon layer. Our results offer a paradigm for controlling electronic characteristics in nanodevices at the future diminutive technology nodes.}, number={29}, journal={JOURNAL OF THE AMERICAN CHEMICAL SOCIETY}, author={He, Tao and Corley, David A. and Lu, Meng and Di Spigna, Neil Halen and He, Jianli and Nackashi, David P. and Franzon, Paul D. and Tour, James M.}, year={2009}, month={Jul}, pages={10023–10030} }
 @inproceedings{hamlett_mcilrath_kiamilev_ozguz_2009, title={CryptoFSM – Securing chips against reverse engineering}, booktitle={Proceedings 2008 Gomactech}, author={Hamlett, M. and McIlrath, L. and Kiamilev, F. and Ozguz, V.}, year={2009}, month={Apr} }
 @inproceedings{thorolffson_gonsalves_franzon_2009, title={Design Automation of a 3DIC FFT Processor, for Synthetic Aperture Radar: A case study}, ISBN={978-1-6055-8497-3}, ISSN={0738-100X}, DOI={10.1145/1629911.1629928}, abstractNote={This work discusses a 1024-point, memory-on-logic 3DIC FFT processor for synthetic aperture radar (SAR), sent to fabrication in the 180 nm MIT Lincoln Labs 3D FDSOI 1.5 V process along with the design flow required to realize it with off-the-shelf commercial 2D tools. The work shows how the vertical dimension can be exploited for novel memory architecture tradeoffs that are not feasible in 2D, reducing the energy consumed per memory operation in the FFT by 60.3%. In comparison to its 2D counterpart, the SAR FFT processor exhibits a 53.0% decrease in average wire length, a 24.6% increase in maximum operating frequency and a 25.3% decrease in total silicon area.}, booktitle={Proceedings ACM/IEEE DAC 2009}, author={Thorolffson, T. and Gonsalves, K. and Franzon, P.D.}, year={2009}, pages={51–56} }
 @inproceedings{melamed_thorolfsson_srinivasan_cheng_franzon_davis_2009, title={Junction-level thermal extraction and simulation of 3DICs}, DOI={10.1109/3DIC.2009.5306529}, abstractNote={In 3DICs heat dissipating devices are stacked directly on top of each other leading to a higher heat density than in a comparable 2D chip. 3D integration also moves the majority of active devices further away from the heatsink. This results in a degraded thermal path which makes it more challenging to remove heat from the active devices. Gradient FireBolt was used to perform an appropriate 3D thermal analysis on a 1024-point, memory-on-logic 3DIC FFT processor for synthetic aperture radar (SAR). The chip was simulated with a spatial resolution of 80 nm, and was modeled to include the effect of each line of interconnect, as well as each via and fill structure exactly as drawn in the layout. Large isolated temperature spikes were found near groups of clock buffers at the edge of the SRAMs on the middle tier. It was found that lowering the simulation resolution and using composite thermal conductivities failed to accurately predict the location of these tentpoles.}, booktitle={2009 IEEE International Conference on 3d Systems Integration}, author={Melamed, S. and Thorolfsson, T. and Srinivasan, A. and Cheng, E. and Franzon, P. and Davis, R.}, year={2009}, pages={395–401} }
 @inproceedings{gadfort_franzon_2009, title={Low-power self-equalizing driver for silicon carrier interconnects with low bit error rate}, DOI={10.1109/epeps.2009.5338482}, abstractNote={This paper demonstrates and compares the power efficiency of a standard differential current mode driver operating over an FR-4 channel with an improved driver with pre-emphasis operating over a silicon carrier channel. The drivers were designed for a 45 nm process, and both achieved a bit error rate of 10−15 errors per bit while operating at 4 Gbps. The power of the improved driver was reduced to one-fourth that of the standard driver through the utilization of the silicon carrier channels and pre-emphasis.}, booktitle={Electrical Performance of Electronic Packaging and Systems}, author={Gadfort, P. and Franzon, Paul}, year={2009}, pages={37–40} }
 @inproceedings{erickson_wilson_chandrasekar_franzon_2009, title={Multi-bit fractional equalization for multi-Gb/s inductively coupled connectors}, DOI={10.1109/epeps.2009.5338463}, abstractNote={Multi-bit fractional equalization at the driver side allows for multi-Gb/s signaling across transformers which suffer from excessive ISI in inductively coupled connectors and backplanes. When an inductively coupled element is place in a transmission line or the gap between inductors in a transformer increases, the amplitude of the coupled pulse is decreased while the natural decay of the pulse is maintained. By removing the effects of the natural decaying tail of the pulse created by coupling an NRZ signal across a transformer, high-speed inductive coupling can be achieved over the larger transformers required by connectors and backplanes.}, booktitle={Electrical Performance of Electronic Packaging and Systems}, author={Erickson, E. and Wilson, J. and Chandrasekar, K. and Franzon, Paul}, year={2009}, pages={121–124} }
 @misc{kumar_reinitz_simunovic_sandeep_franzon_2009, title={Overview of RFID Technology and Its Applications in the Food Industry}, volume={74}, ISSN={["1750-3841"]}, DOI={10.1111/j.1750-3841.2009.01323.x}, abstractNote={ABSTRACT:  Radio frequency identification (RFID) is an alternative technology with a potential to replace traditional universal product code (UPC) barcodes. RFID enables identification of an object from a distance without requiring a line of sight. RFID tags can also incorporate additional data such as details of product and manufacturer and can transmit measured environmental factors such as temperature and relative humidity. This article presents key concepts and terminology related to RFID technology and its applications in the food industry. Components and working principles of an RFID system are described. Numerous applications of RFID technology in the food industry (supply chain management, temperature monitoring of foods, and ensuring food safety) are discussed. Challenges in implementation of RFID technology are also discussed in terms of read range, read accuracy, nonuniform standards, cost, recycling issues, privacy, and security concerns.}, number={8}, journal={JOURNAL OF FOOD SCIENCE}, author={Kumar, P. and Reinitz, H. W. and Simunovic, J. and Sandeep, K. P. and Franzon, P. D.}, year={2009}, month={Oct}, pages={R101–R106} }
 @inbook{franzon_2009, title={Use of AC Coupled Interconnect in Contactless Packaging}, booktitle={Coupled Data Communications}, publisher={Springer-Verlag}, author={Franzon, P.}, editor={Ho, RonEditor}, year={2009} }
 @inproceedings{su_patel_hunter_cases_franzon_2008, title={AC coupled backplane communication using embedded capacitor}, ISBN={9781424428731}, url={http://dx.doi.org/10.1109/epep.2008.4675938}, DOI={10.1109/epep.2008.4675938}, abstractNote={Surface mount capacitors can be replaced with a buried capacitor in backplane interconnect applications requiring blocking capacitance, such as FiberChannel. This replacement improves cost, reliability and parasitic inductance. The smaller nominal capacitance value can be compensated for by using an equalizing receiver filter. Tradeoffs in capacitance choice are explained in detail. A nominal capacitance of around 1 pF provides a good choice for the analyzed scenarios.}, booktitle={2008 IEEE-EPEP Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Su, Bruce and Patel, Pravin and Hunter, Steve W. and Cases, Moises and Franzon, Paul D.}, year={2008}, month={Oct} }
 @inproceedings{davis_sule_franzon_2008, title={An 8192-point fast fourier transform 3D-IC case study}, ISBN={9781424421664}, url={http://dx.doi.org/10.1109/mwscas.2008.4616830}, DOI={10.1109/mwscas.2008.4616830}, abstractNote={3D stacking and integration can provide system advantages. This paper explores an application driver for 3D ICs. Interconnect-rich applications especially benefit, sometimes up to the equivalent of two technology nodes. Another promising application area is that of logic-on-memory. This paper presents a case studies of an 8192-point fast Fourier transform (FFT) processor in order to quantify the benefit of the through-silicon vias in an available 180 nm 3D process. The FFT shows a 22% reduction in cycle-time, coupled with an 18% reduction in energy per transform.}, booktitle={2008 51st Midwest Symposium on Circuits and Systems}, publisher={IEEE}, author={Davis, W. Rhett and Sule, Ambarish M. and Franzon, Paul D.}, year={2008}, month={Aug}, pages={438–441} }
 @inproceedings{choi_braunisch_aygun_franzon_2008, title={Analysis of inter-bundle crosstalk in multimode signaling for high-density interconnects}, ISBN={9781424422302}, url={http://dx.doi.org/10.1109/ectc.2008.4550043}, DOI={10.1109/ectc.2008.4550043}, abstractNote={While the increasing demand for smaller packages and low-cost platforms aggressively drives the interconnect density per unit area, crosstalk noise due to capacitive and inductive coupling limits the achievable interconnect density. As an alternative, we investigate multimode signaling where n signals are transmitted by exciting all fundamental modes on a group of n closely coupled lines called a bundle. Even though crosstalk is ideally zero in a single bundle, practical implementation of this idea for a typical input/output (IO) bus requires multiple closely-placed bundles. Thus, inter-bundle crosstalk may be an issue. In this paper, we analyze the inter-bundle crosstalk starting with the analytical expressions for the modal conversion from one bundle to another. Frequency domain simulations for both frequency-dependent and frequency-independent terminations are performed to compare performance vs. density benefits of multi-bundle multi-mode interconnects to those provided by conventional single-ended and differential signaling.}, booktitle={2008 58th Electronic Components and Technology Conference}, publisher={IEEE}, author={Choi, Yongjin and Braunisch, Henning and Aygun, Kemal and Franzon, Paul D.}, year={2008}, month={May} }
 @inproceedings{yadav_jenkal_franzon_lafucci_potts_burgess_2008, title={Application Specific Integrated Circuit Verification: An Illustration Based Approach}, booktitle={IEEE MSE}, author={Yadav, M. and Jenkal, R. and Franzon, P. and Lafucci, P. and Potts, B. and Burgess, I.}, year={2008}, month={May} }
 @inproceedings{franzon_davis_steer_hao_lipa_luniya_mineo_oh_sule_thorolfsson_2008, title={Application and Design Exploration for 3D Integrated Circuits}, booktitle={VLSI Multi-level Interconnect Conference}, author={Franzon, Paul D. and Davis, William Rhett and Steer, Michael B. and Hao, Hua and Lipa, Steven and Luniya, Sonali and Mineo, Christopher and Oh, Julie and Sule, Ambirish and Thorolfsson, Thor}, year={2008}, month={Sep} }
 @inproceedings{pitts_vaidya_kadambi_malkani_franzon_2008, title={Autonomous Vision Processing and 3D Scene Reconstruction}, booktitle={GOMACTECH}, author={Pitts, W.S. and Vaidya, M. and Kadambi, M. and Malkani, S. and Franzon, P.D.}, year={2008}, month={Apr} }
 @inproceedings{franzon_2008, title={Computer-Aided Design and Application Exploration for 3D Integrated Circuits}, booktitle={GOMACTECH}, author={Franzon, P.D.}, year={2008}, month={Apr} }
 @inproceedings{franzon_berkeley_shani_obermiller_davis_steer_lipa_oh_thorolfsson_melamed_et al._2008, title={Design and CAD for 3D integrated circuits}, ISBN={9781605581156}, url={http://dx.doi.org/10.1145/1391469.1391642}, DOI={10.1145/1391469.1391642}, abstractNote={High density through silicon vias (TSV) can be used to build 3DICs that enable unique applications in computing, signal processing and memory intensive systems. This paper presents several case studies that are uniquely enhanced through 3D implementation, including a 3D CAM, an FFT processor, and a SAR processor. The CAD flow used to implement for these designs is described. 3DIC requires higher fidelity thermal modeling than 2DIC design. The rationale for this requirement is established and a possible solution is presented.}, booktitle={Proceedings of the 45th annual conference on Design automation - DAC '08}, publisher={ACM Press}, author={Franzon, Paul D. and Berkeley, Stephen and Shani, Ben and Obermiller, Kurt and Davis, W. Rhett and Steer, Michael B. and Lipa, Steve and Oh, Eun Chu and Thorolfsson, Thor and Melamed, Samson and et al.}, year={2008}, pages={668–673} }
 @inbook{franzon_2008, title={Design for 3-D Integration}, booktitle={3-D IC Integration: Technology and Applications}, publisher={Wiley VCH}, author={Franzon, P.}, editor={Garrou, P. and Ramm, P. and Bower, C.Editors}, year={2008}, month={May} }
 @inproceedings{pitts_devasthali_damiano_franzon_2008, title={Extreme Temperature Invariant Circuitry Through Adaptive Body Biasing}, booktitle={GOMACTECH}, author={Pitts, W.S. and Devasthali, V. and Damiano, J. and Franzon, P.D.}, year={2008}, month={Apr} }
 @article{canavero_franzon_2008, title={Foreword Special Section on Electrical Performance Analysis and Simulation of Interconnects, Packages and Devices Composing Electronic Systems for High-Performance Applications}, volume={31}, ISSN={["1521-3323"]}, DOI={10.1109/tadvp.2008.2009342}, abstractNote={The eleven papers in this spection section are devoted to electrical performance analysis and simulation of interconnects, packages and devices composing electronic systems for high-performance applications.}, number={4}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Canavero, Flavio and Franzon, Paul D.}, year={2008}, month={Nov}, pages={662–663} }
 @article{varma_steer_franzon_2008, title={Improving Behavioral IO Buffer Modeling Based on IBIS}, volume={31}, ISSN={["1521-3323"]}, DOI={10.1109/tadvp.2008.2004995}, abstractNote={High level behavioral modeling is widely used in lieu of low level transistor models to ascertain the behavior of input/output (IO) drivers and receivers. The input output buffer information specification (IBIS) is one of the most widely used methodologies to model IO drivers as it satisfies the basic requirements of a behavioral model such as IP protection, simple structure, fast simulation time, and reasonable accuracy. As driver technology gets increasingly complicated and rise time of input signal gets increasingly smaller, important considerations such as simultaneous switching noise (SSN) becomes a major consideration when simulating multiple IO drivers in the integrated circuit. Unfortunately, IBIS falls short of becoming a complete IO behavioral model when simulating for SSN. This paper addresses the problem by assessing what is missing in IBIS. A method is presented for compensating for the missing information by complimenting the IBIS model with a black box that is simulator independent, without compromising with the speed that IBIS enjoys over the transistor models.}, number={4}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Varma, Ambrish K. and Steer, Michael and Franzon, Paul D.}, year={2008}, month={Nov}, pages={711–721} }
 @inproceedings{chandrasekar_wilson_erickson_feng_xu_mick_franzon_2008, title={Inductively coupled connectors and sockets for multi-Gb/s pulse signaling}, volume={31}, DOI={10.1109/tadvp.2008.2005465}, abstractNote={Multi-Gb/s pulse signaling is demonstrated with inductively coupled interconnects across packaging interfaces. This has application in realizing submillimeter pitch, true zero insertion force (ZIF) surface mount connectors, and sockets. The signaling data rate achieved in this system is from 1 to 8.5 Gbps, which depends on the 3-dB coupling frequency of the composite channel consisting of the inductive interconnections and the transmission lines. This paper presents the results of a set of experiments demonstrating this capability and describes the principles behind the design of inductively coupled sockets and connectors.}, number={4}, booktitle={IEEE Transactions on Advanced Packaging}, author={Chandrasekar, K. and Wilson, J. and Erickson, E. and Feng, Z. P. and Xu, J. and Mick, S. and Franzon, Paul}, year={2008}, pages={749–758} }
 @inproceedings{puri_varma_edwards_weger_franzon_yang_kosonocky_2008, title={Keeping hot chips cool}, ISBN={9781605581156}, url={http://dx.doi.org/10.1145/1391469.1391632}, DOI={10.1145/1391469.1391632}, abstractNote={Thermal issues are becoming more important but is the hype getting the better of the facts? Does this deserve more attention than for some niche designs and technologies such as 3D ICs.? Does the broader design community need to worry about it at 32 nm and beyond or it will only impact a small segment of designs? In short, does the severity of power issues coupled with packaging complexity translate into a thermal crisis in future? This is an educational panel with a little bit of controversy that will address the thermal issue in IC design. When will this issue be emerging as a crucial concern if at all? What are the solutions to resolve this potential crisis?}, booktitle={Proceedings of the 45th annual conference on Design automation - DAC '08}, publisher={ACM Press}, author={Puri, Ruchir and Varma, Devadas and Edwards, Darvin and Weger, Alan J and Franzon, Paul and Yang, Andrew and Kosonocky, Stephen}, year={2008} }
 @inproceedings{franzon_lipa_oh_thorolfsson_davis_2008, title={Memory rich applications for 3D integration}, url={http://dx.doi.org/10.1117/12.810061}, DOI={10.1117/12.810061}, abstractNote={3D stacking and integration can provide system advantages equivalent to up to two technology nodes of scaling. This paper explores memory rich applications for 3DIC. It shows how memory power and memory bandwidth can both be improved by an order of magnitude through 3D integration, and specifically explores a DSP application.}, booktitle={Smart Structures, Devices, and Systems IV}, publisher={SPIE}, author={Franzon, Paul D. and Lipa, Steven and Oh, Julie and Thorolfsson, Thor and Davis, Rhett}, editor={Al-Sarawi, Said F. and Varadan, Vijay K. and Weste, Neil and Kalantar-Zadeh, KouroshEditors}, year={2008}, month={Dec} }
 @inproceedings{choi_won_franzon_braunisch_aygun_2008, title={Multimode signaling on non-ideal channels}, DOI={10.1109/epep.2008.4675874}, abstractNote={Simultaneous optimization of interconnect density and crosstalk poses conflicting requirements with conventional differential signaling. As an alternative, we investigate multimode signaling where n signals are transmitted by exciting all fundamental modes on a group of n closely located lines. In this paper, the channel response of multimode signaling is analyzed to demonstrate the benefits of this signaling. The misaligned channel and length mismatch sensitivity of multimode signaling are also analyzed.}, booktitle={2008 IEEE-EPEP Electrical Performance of Electronic Packaging}, author={Choi, Yongjin and Won, Chanyoun and Franzon, Paul D. and Braunisch, Henning and Aygun, Kemal}, year={2008}, month={Oct}, pages={51–54} }
 @article{he_lu_yao_he_chen_di spigna_nackashi_franzon_tour_2008, title={Reversible Modulation of Conductance in Silicon Devices via UV/Visible-Light Irradiation}, volume={20}, ISSN={["1521-4095"]}, DOI={10.1002/adma.200703084}, abstractNote={,}, number={23}, journal={ADVANCED MATERIALS}, author={He, Tao and Lu, Meng and Yao, Jun and He, Jianli and Chen, Bo and Di Spigna, Neil Halen and Nackashi, David P. and Franzon, Paul D. and Tour, James M.}, year={2008}, month={Dec}, pages={4541–4546} }
 @article{xie_cong_franzon_2008, title={Special issue on 3D integrated circuits and microarchitectures}, volume={4}, DOI={10.1145/1412587.1412588}, abstractNote={This special issue of the ACM Journal of Emerging Technologies in Computing Systems is dedicated to three-dimensional integrated circuits and microarchitectures. Three-dimensional (3D) Integrated Circuits have emerged as an attractive option for overcoming the barriers in interconnect scaling. To efficiently exploit the benefits of 3D technologies, design techniques and methodologies for supporting 3D designs are imperative; design space exploration at the architectural level is also essential to fully take advantage of the 3D integration technologies and build a high performance chip. A call for papers for the JETC special issue was announced in August 2007. All submissions went through the regular review process of JETC. After review and appropriate revisions, five papers on diverse topics related to 3D integration were accepted for the special issue. In the first article of this special issue, Kgil et al. describe a new architecture design called PicoServer, which employs 3D technology to bond ChipMultiprocessors (CMPs) die to multiple DRAM memory dies sufficient for a primary memory. The use of 3D stacks facilitates wide low-latency buses between processors and memory and removes the need for L2 caches. Such architecture enables the design of compact and energy efficient servers. The second article by Ma et al. explores fine-granularity 3D integration and its impact on the microarchitecture design. The authors study the multilayer block implementation alternatives and propose a microarchitecture-physical codesign framework to perform thermal-aware cooptimization of microarchitecture design and physical design. It also demonstrates that thermal-aware design planning and the use of thermal vias can help mitigate the temperature increases due to vertical integration. The third article by Zhan and Sapatnekar presents a design automation solution for power delivery in 3D IC. A partition-based algorithm is proposed to assign modules to different Vdd domains in a two-level stacked-Vdd circuit. In the fourth article, Ferri et al. study the impact of process variations on the performance and parametric yield of 3D ICs and provide integration strategies that maximize the parametric yield. Finally, in the fifth article, Miyakawa et al. present a 3D stacking technology developed by Honda Research Institute. The process steps for this wafer-to-wafer stacking method are described in detail. A prototype of a 3-layer stacking chip is fabricated using 0.18μm CMOS technology based on 8-inch wafers. The 3-layer prototype chip consists of a microprocessor layer, a memory layer, and a custom logic layer. We would like to thank all the authors who responded to the call for papers and the reviewers who provided detailed and insightful reviews in a timely}, number={4}, journal={ACM Journal on Emerging Technologies in Computing Systems}, author={Xie, Y. and Cong, J. and Franzon, Paul}, year={2008} }
 @inproceedings{franzon_davis_steer_hao_lipa_luniya_mineo_oh_sule_thorolfsson_2007, title={Application and Design Exploration for 3D Integrated Circuits}, booktitle={VLSI Multi-level Interconnect Conference}, author={Franzon, Paul D. and Davis, William Rhett and Steer, Michael B. and Hao, Hua and Lipa, Steven and Luniya, Sonali and Mineo, Christopher and Oh, Julie and Sule, Ambirish and Thorolfsson, Thor}, year={2007}, month={Sep} }
 @inproceedings{oh_franzon_2007, title={Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory}, ISBN={9781424407866}, url={http://dx.doi.org/10.1109/cicc.2007.4405801}, DOI={10.1109/cicc.2007.4405801}, abstractNote={Three dimensional (3D) ternary content addressable memory (TCAM) has been designed in a 0.18 mum fully depleted silicon on insulator (FD SOI) 3D IC process. This paper demonstrates that a 3D TCAM with three tiers can achieve 40% matchline capacitance reduction and 21% power reduction compared to a TCAM in a conventional single-tier process. This paper also discusses design considerations of 3D TCAM including partitioning methods for multiple tiers and layout methods of interconnects.}, booktitle={2007 IEEE Custom Integrated Circuits Conference}, publisher={IEEE}, author={Oh, Eun Chu and Franzon, Paul D.}, year={2007}, month={Sep} }
 @inproceedings{franzon_davis_steer_hao_lipa_luniya_mineo_oh_sule_thorolfsson_et al._2007, title={Design for 3D Integration and Applications}, ISBN={1424414482 1424414490}, url={http://dx.doi.org/10.1109/issse.2007.4294463}, DOI={10.1109/issse.2007.4294463}, abstractNote={3D stacking and integration can provide system advantages equivalent to up to two technology nodes of scaling. This paper explores application drivers and computer aided design (CAD) for 3D ICs.}, booktitle={2007 International Symposium on Signals, Systems and Electronics}, publisher={IEEE}, author={Franzon, Paul and Davis, William Rhett and Steer, Michael B. and Hao, Hua and Lipa, Steven and Luniya, Sonali and Mineo, Christopher and Oh, Julie and Sule, Ambirish and Thorolfsson, Thor and et al.}, year={2007}, month={Jul}, pages={263–266,} }
 @article{blum_soto_wilson_amsinck_franzon_ratna_2007, title={Electronic properties of molecular memory circuits on a nanoscale scaffold}, volume={6}, ISSN={["1558-2639"]}, DOI={10.1109/TNB.2007.908978}, abstractNote={Significant challenges exist in assembling and interconnecting the building blocks of a nanoscale device and being able to electronically address or measure responses at the molecular level. Here we demonstrate the usefulness of engineered proteins as scaffolds for bottom-up self-assembly for building nanoscale devices out of multiple components. Using genetically engineered cowpea mosaic virus, modified to express cysteine residues on the capsid exterior, gold nanoparticles were attached to the viral scaffold in a specific predetermined pattern to produce specific interparticle distances. The nanoparticles were then interconnected using thiol-terminated conjugated organic molecules, resulting in a three-dimensional network. Network properties were engineered by using molecular components with different I-V characteristics. Networks consisting of molecular wires alone were compared with networks containing voltage controlled molecular switches with two stable conductance states. Using such bistable molecules enabled the formation of switchable molecular networks that could be used in nanoscale memory circuits.}, number={4}, journal={IEEE TRANSACTIONS ON NANOBIOSCIENCE}, author={Blum, Amy Szuchmacher and Soto, Carissa M. and Wilson, Charmaine D. and Amsinck, Christian and Franzon, Paul and Ratna, Banahalli R.}, year={2007}, month={Dec}, pages={270–274} }
 @inproceedings{pazhayaveetil_chandra_franzon_2007, title={Flexible Low Power Probability Density Estimation Unit For Speech Recognition}, ISBN={1424409209 1424409217}, url={http://dx.doi.org/10.1109/iscas.2007.378206}, DOI={10.1109/iscas.2007.378206}, abstractNote={This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a large vocabulary speech recognition system, and targeted for mobile platforms. The speech recognition system is based on hidden Markov models and consists of two computationally intensive parts - the probability density estimation using Gaussian distributions, and the Viterbi decoding. The power hungry nature of these computations prevents porting the application successfully to mobile devices. We have designed a flexible probability estimation unit that is both power efficient and meets real time requirements while being flexible enough to handle emerging speech recognition techniques. The flexible nature of the design allows it to utilize emerging power and computation reduction techniques (at the algorithm level) to achieve up to an 80% power reduction as compared to conventional designs}, booktitle={2007 IEEE International Symposium on Circuits and Systems}, publisher={IEEE}, author={Pazhayaveetil, Ullas and Chandra, Dhruba and Franzon, Paul}, year={2007}, month={May} }
 @inproceedings{stine_castellanos_wood_henson_love_davis_franzon_bucher_basavarajaiah_oh_et al._2007, title={FreePDK: An Open-Source Variation-Aware Design Kit}, ISBN={076952849X}, url={http://dx.doi.org/10.1109/mse.2007.44}, DOI={10.1109/mse.2007.44}, abstractNote={This paper discusses an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45 nm,for use in VLSI research, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation and perform statistical circuit analysis. The kit also includes a standard cell and pad library with the necessary support files to enable full chip place and route and verification for System on Chip designs. Test chips designed with this PDK are designed in such a way so that they can be fabricated by fabrication facilities allowing validation of the design rules so that the rules may be used in future multi-project runs and design contests.}, booktitle={2007 IEEE International Conference on Microelectronic Systems Education (MSE'07)}, publisher={IEEE}, author={Stine, James E. and Castellanos, Ivan and Wood, Michael and Henson, Jeff and Love, Fred and Davis, W. Rhett and Franzon, Paul D. and Bucher, Michael and Basavarajaiah, Sunil and Oh, Julie and et al.}, year={2007}, month={Jun} }
 @article{wilson_mick_xu_luo_bonafede_huffman_labennett_franzon_2007, title={Fully integrated AC coupled interconnect using buried bumps}, volume={30}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2007.896920}, abstractNote={Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.}, number={2}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Wilson, John and Mick, Stephen and Xu, Jian and Luo, Lei and Bonafede, Salvatore and Huffman, Alan and LaBennett, Richard and Franzon, Paul D.}, year={2007}, month={May}, pages={191–199} }
 @inproceedings{yadav_venkatachaliah_franzon_2007, title={Hardware Architecture of a Parallel Pattern Matching Engine}, ISBN={1424409209 1424409217}, url={http://dx.doi.org/10.1109/iscas.2007.378482}, DOI={10.1109/iscas.2007.378482}, abstractNote={Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This process of pattern matching at line speeds is a memory and computation intensive task. Hence, it requires dedicated hardware algorithms. This paper describes the hardware architecture of a parallel, pipelined pattern matching engine that uses trie based pattern matching algorithmic approach. The algorithm optimizes pattern matching process through two key innovations of parallel pattern matching using incoming content filter and multiple character matching using trie pruning. The hardware implementation is capable of performing at line-speeds and handle traffic rates up to OC-192, the underlying architecture allows for multiple patterns to be detected and for the system to gracefully recover from a failed partial match, the throughput of the system does not degrade with the increase in the number of patterns or the length of the patterns to be matched. The solution described outperforms most current implementations in terms of speed and memory requirement and outperforms TCAM based solutions in terms of power consumption, area, and cost while remaining competitive in terms of throughput and update times. The complete Snort rule set (2005 release) and VoIP RFC were used to validate our performance and achieve a throughput of 12Gbps with 6KBytes of content filter memory and 0.3 MBytes of total memory for Snort and 0.5KBytes of filter memory and 12KBytes of total memory for SIP.}, booktitle={2007 IEEE International Symposium on Circuits and Systems}, publisher={IEEE}, author={Yadav, Meeta and Venkatachaliah, Ashwini and Franzon, Paul D.}, year={2007}, month={May} }
 @inproceedings{franzon_amsinck_dispigna_nackashi_sonkusale_2007, title={Molecular Electronics}, booktitle={2nd IEEE International Workshop on advances in sensors and interfaces}, author={Franzon, P. and Amsinck, C. and DiSPigna, N.H. and Nackashi, D. and Sonkusale, S.}, year={2007}, month={Jun} }
 @inbook{franzon_nackashi_amsinck_dispigna_sonkulale_2007, title={Molecular Electronics – Devices and Circuits Technology}, booktitle={Vlsi-Soc: From Systems To Silicon}, publisher={Springer Boston}, author={Franzon, P.D. and Nackashi, D. and Amsinck, C. and DiSpigna, N. and Sonkulale, S.}, year={2007}, month={Oct} }
 @article{yuce_liu_damiano_bharath_franzon_dogan_2007, title={SOI CMOS implementation of a multirate PSK demodulator for space communications}, volume={54}, ISSN={["1558-0806"]}, DOI={10.1109/TCSI.2006.885988}, abstractNote={A low-power phase-shift keying demodulator integrated circuit (IC) has been implemented using silicon-on-insulator CMOS technology for deep space and satellite applications. The demodulator employs double differential detection to increase its robustness to the Doppler shift caused by the movement of the space vehicle and sampling technique with 1-bit analog-to-digital converter (ADC) at the front to reduce the complexity and power dissipation. In particular, digital decimation is used after sampling to achieve a low power implementation of multirate transmission. Operating at ultra-high-frequency (435 MHz), the receiver system supports a wide range of data rates (0.1-100 Kbps). From test results, the power consumption of the demodulator circuit including the 1-bit ADC is below 1 mW for data rates up to 100 Kbps}, number={2}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS}, author={Yuce, Mehmet Rasit and Liu, Wentai and Damiano, John and Bharath, Bhaskar and Franzon, Paul D. and Dogan, Numan S.}, year={2007}, month={Feb}, pages={420–431} }
 @inproceedings{thorolfsson_franzon_2007, title={System Design for 3D Multi-FPGA Packaging}, ISBN={9781424408832}, url={http://dx.doi.org/10.1109/epep.2007.4387152}, DOI={10.1109/epep.2007.4387152}, abstractNote={3D stacking and integration can provide tremendous advantages to electronic systems. This paper explores the system-level considerations such as layout, routing and IO in the design of 3D multi-FPGA packaging, along with their architectural implications.}, booktitle={2007 IEEE Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Thorolfsson, Thorlindur and Franzon, Paul D.}, year={2007}, month={Oct} }
 @inproceedings{varma_steer_franzon_2007, title={System level Validation of Improved IO Buffer Behavioral Modeling Methodology Based on IBIS}, ISBN={9781424408832}, url={http://dx.doi.org/10.1109/epep.2007.4387200}, DOI={10.1109/epep.2007.4387200}, abstractNote={System level simulation and validation of a new macromodeling methodology based on IBIS (Input/Output Buffer Information Specification) models is presented. Enhancements of the black-box techniques discussed in [1] are discussed. The proposed macromodel is circuit based and can be customized by model makers or users. The new macromodel produces models that can be simulated accurately for Simultaneous Switching Noise (SSN). To demonstrate the solution, a CMOS voltage-mode driver circuit and a MICRON DDR2 driver are simulated using real life package models and compared with equivalent circuits created with IBIS models of the same drivers.}, booktitle={2007 IEEE Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Varma, Ambrish and Steer, Michael and Franzon, Paul}, year={2007}, month={Oct} }
 @article{sonkusale_di spigna_franzon_2007, title={Uniformity analysis of wafer scale sub-25 nm wide nanowire array nanoimprint mold fabricated by PEDAL process}, volume={84}, ISSN={["0167-9317"]}, DOI={10.1016/j.mee.2007.01.210}, abstractNote={In earlier publications [S. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson, P.D. Franzon, E. Physica, Low Dimensional Systems and Nanostructures 28 (2005) 107–114; S. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson, P.D. Franzon, in: Proceedings of Nano Science and Technology Institute (NSTI) conference 2005, vol. 3, pp. 255.], we proposed and successfully demonstrated an unconventional lithographic technique called PEDAL process (planar edge defined alternate layer) to define wafer scale sub 25 nm nanowires and nanoimprint template. In this publication, the uniformity results on array of sixteen line-width structures with obtained by PEDAL process are presented. The average pitch of array across the 4 in. wafer was measured to be 40.8 nm with the standard deviation of 2.3 nm where as the average pitch of the lines in an array was found to be 41.5 nm with the standard deviation of 4.6 nm. After Pd lift-off the average pitch in nanowire array was measured to be 41.9 nm with standard deviation of 1.8 nm, which is close to the values obtained for the template.}, number={5-8}, journal={MICROELECTRONIC ENGINEERING}, author={Sonkusale, Sachin R. and Di Spigna, Neil H. and Franzon, Paul D.}, year={2007}, pages={1523–1527} }
 @article{zhang_wilson_bashirullah_luo_xu_franzon_2007, title={Voltage-mode driver preemphasis technique for on-chip global buses}, volume={15}, ISSN={["1557-9999"]}, DOI={10.1109/TVLSI.2007.893588}, abstractNote={This paper demonstrates that driver preemphasis technique can be used for on-chip global buses to increase signal channel bandwidth. Compared to conventional repeater insertion techniques, driver preemphasis saves repeater layout complexity and reduces power consumption by 12%-39% for data activity factors above 0.1. A driver circuit architecture using voltage-mode preemphasis technique was tested in 0.18-mum CMOS technology for 10-mm long interconnects at 2 Gb/s}, number={2}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Zhang, Liang and Wilson, John M. and Bashirullah, Rizwan and Luo, Lei and Xu, Jian and Franzon, Paul D.}, year={2007}, month={Feb}, pages={231–236} }
 @article{luo_wilson_mick_xu_zhang_franzon_2006, title={3 Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver}, volume={41}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/jssc.2005.859881}, DOI={10.1109/jssc.2005.859881}, abstractNote={A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.}, number={1}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Luo, L. and Wilson, J.M. and Mick, S.E. and Xu, J. and Zhang, L. and Franzon, P.D.}, year={2006}, month={Jan}, pages={287–296} }
 @inproceedings{zhang_wilson_bashirullah_luo_xu_franzon_2006, title={A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling}, ISBN={1424400759}, url={http://dx.doi.org/10.1109/cicc.2006.320855}, DOI={10.1109/cicc.2006.320855}, abstractNote={A 16-bit on-chip bus with driver pre-emphasis fabricated in 0.25mum CMOS technology attains an aggregate signaling data rate of 32Gb/s over 5-10mm long lossy interconnects while reducing delay latency by 28.3%, power by 15.0%, and peak current by 70% over a conventional single-ended voltage-mode static bus. The proposed bus is robust against crosstalk noise and occupies comparable routing area to a reference static bus design}, booktitle={IEEE Custom Integrated Circuits Conference 2006}, publisher={IEEE}, author={Zhang, Liang and Wilson, John and Bashirullah, Rizwan and Luo, Lei and Xu, Jian and Franzon, Paul}, year={2006}, month={Sep} }
 @inproceedings{luo_wilson_mick_xu_zhang_erickson_franzon_2006, title={A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver}, ISBN={1424400767 1424400759}, url={http://dx.doi.org/10.1109/cicc.2006.320976}, DOI={10.1109/cicc.2006.320976}, abstractNote={A new differential pulse receiver is demonstrated for AC coupled interconnect (ACCI), which enables the highest data rate, at 6Gb/s/channel (36Gb/s aggregate), for capacitively coupled systems using pulse signaling. The system works across FR4 printed circuit board (PCB) interconnect lengths of up to 30cm with coupling capacitors from 95fF to 165fF, while dissipating only 1.97mW/Gbps for the entire differential transceiver (0.83pJ/bit for the transmitter and 1.23pJ/bit for the receiver)}, booktitle={IEEE Custom Integrated Circuits Conference 2006}, publisher={IEEE}, author={Luo, Lei and Wilson, John and Mick, Stephen and Xu, Jian and Zhang, Liang and Erickson, Evan and Franzon, Paul}, year={2006}, month={Sep} }
 @inproceedings{wilson_luo_mick_chan_lin_franzon_2006, title={AC Coupled Interconnect using Buried Bumps for Laminated Organic Packages}, booktitle={Proceedings Electronic Components and Technology, ECTC}, author={Wilson, J. and Luo, L. and Mick, S. and Chan, B. and Lin, H. and Franzon, P.}, year={2006} }
 @inproceedings{chandra_pazhayaveetil_franzon_2006, title={Architecture for Low Power Large Vocabulary Speech Recognition}, ISBN={0780397827 0780397819}, url={http://dx.doi.org/10.1109/socc.2006.283836}, DOI={10.1109/socc.2006.283836}, abstractNote={This paper proposes an architecture for real-time large vocabulary speech recognition on a mobile embedded device. The speech recognition system is based on Hidden Markov Model (HMM), which involves complex mathematical operations such as probability estimation and Viterbi decoding. This computational nature makes it power hungry and realtime recognition is not achieved by porting software solutions on embedded device. Our system architecture has a low power embedded processor and dedicated ASIC units for complex computations. These units operate at a low frequency of 50 MHz thus consuming low power. The system uses RAM for the intermediate values and flash memory to store acoustic and language models for speech recognition.}, booktitle={2006 IEEE International SOC Conference}, publisher={IEEE}, author={Chandra, Dhruba and Pazhayaveetil, Ullas and Franzon, Paul}, year={2006}, month={Sep} }
 @inproceedings{wilson_mick_xu_luo_erickson_franzon_2006, title={Considerations for Transmission Line Design on MCMs using AC Coupled Interconnect with Buried Solder Bumps}, ISBN={1424404541}, url={http://dx.doi.org/10.1109/spi.2006.289245}, DOI={10.1109/spi.2006.289245}, abstractNote={AC coupled interconnect (ACCI) using buried solder bumps is a technology that provides a complete interconnect and packaging solution by integrating high-density, low inductance power and ground distribution with high-density, high-speed I/O. The mixture of solder bump technology and AC coupled I/O has the potential to improve yield during packaging and assembly since I/O channels are no longer dependent on the yield of a single solder bump. For the same reason, this technology has the potential to increase the long-term reliability of chip/carrier components of electronic systems used in harsh environments (e.g. extreme vibration, shock, and temperature variation). An important consideration in systems using this technology is how the electrical properties of transmission line are altered when it is routed beneath a die that is in close proximity (< 5 mum) to the surface of the substrate}, booktitle={2006 IEEE Workship on Signal Propagation on Interconnects}, publisher={IEEE}, author={Wilson, J.M. and Mick, S. E. and Xu, J. and Luo, L. and Erickson, E. L. and Franzon, P.D.}, year={2006}, month={May} }
 @article{he_he_lu_chen_pang_reus_nolte_nackashi_franzon_tour_et al._2006, title={Controlled modulation of conductance in silicon devices by molecular monolayers}, volume={128}, ISSN={["1520-5126"]}, DOI={10.1021/ja063571l}, abstractNote={We have controllably modulated the drain current (I(D)) and threshold voltage (V(T)) in pseudo metal-oxide-semiconductor field-effect transistors (MOSFETs) by grafting a monolayer of molecules atop oxide-free H-passivated silicon surfaces. An electronically controlled series of molecules, from strong pi-electron donors to strong pi-electron acceptors, was covalently attached onto the channel region of the transistors. The device conductance was thus systematically tuned in accordance with the electron-donating ability of the grafted molecules, which is attributed to the charge transfer between the device channel and the molecules. This surface grafting protocol might serve as a useful method for controlling electronic characteristics in small silicon devices at future technology nodes.}, number={45}, journal={JOURNAL OF THE AMERICAN CHEMICAL SOCIETY}, author={He, T. and He, J. L. and Lu, M. and Chen, B. and Pang, H. and Reus, W. F. and Nolte, W. M. and Nackashi, D. P. and Franzon, Paul and Tour, J. M. and et al.}, year={2006}, month={Nov}, pages={14537–14541} }
 @inproceedings{sonkusale_franzon_2006, title={Controlled nanowire fabrication by PEDAL process}, ISBN={1424403901 142440391X}, url={http://dx.doi.org/10.1109/nanonet.2006.346225}, DOI={10.1109/nanonet.2006.346225}, abstractNote={In earlier publications, the authors proposed and successfully demonstrated an unconventional lithographic technique called PEDAL process (planar edge defined alternate layer) to define wafer scale sub 25 nm nanowires and nanoimprint template. In this publication, uniformity analysis of the width and spacing of an array of sixteen line-width structures with approximately 42 nm pitch and twenty four line-width structures with approximately 23 nm pitch, fabricated by PEDAL process, is presented. Results on routing capability of this process along with results of palladium nanowires obtained by PEDAL lift-off process done on the template with 42 nm pitch is also reported. In the case of template with array of sixteen lines, the average pitch of array across the 4 inch wafer was measured to be 40.83 nm with the standard deviation of 2.29 nm where as the average pitch of the lines in an array was found to be 41.5 nm with the standard deviation of 4.64 nm. After Pd liftoff the average pitch in nanowire array was measured to be 41.88 nm with standard deviation of 1.83 nm, close to the values obtained for the template. In the case of array of twenty four line-widths, average pitch of array across the 4 inch wafer was measured to be 21.1 nm with the standard deviation of 5 A where as the average pitch of the line in an array was found to be 22.6 nm with the standard deviation of 9 A. The experimental results presented in this paper prove the efficacy of PEDAL process in making nanowire template of sub-25 nm wide lines with good routing capability}, booktitle={2006 1st International Conference on Nano-Networks and Workshops}, publisher={IEEE}, author={Sonkusale, Sachin and Franzon, Paul}, year={2006}, month={Sep} }
 @article{di spigna_nackashi_amsinck_sonkusale_franzon_2006, title={Deterministic nanowire fanout and interconnect without any critical translational alignment}, volume={5}, ISSN={["1941-0085"]}, DOI={10.1109/TNANO.2006.876926}, abstractNote={Interfacing the nanoworld with the microworld represents a critical challenge to fully integrated nanosystems. Solutions to this problem have generally required either nanoprecision alignment or stochastic assembly. A design is presented that allows complete and deterministic fanout of regular arrays of wires from the nano- to the microworld without the need for any critical translational alignment steps. For example, deterministically connecting 10-nm wires directly to 3-mum wires would require a translational alignment to within only about 6 mum. The design also allows for nanowire interconnect and is independent of the technology used to fabricate the nanowires, enabling technologies for which alignment remains very challenging. The impact of potential fabrication errors is analyzed and a structure is fabricated that demonstrates the feasibility of such a design}, number={4}, journal={IEEE TRANSACTIONS ON NANOTECHNOLOGY}, author={Di Spigna, Neil H. and Nackashi, David P. and Amsinck, Christian J. and Sonkusale, Sachin R. and Franzon, Paul D.}, year={2006}, month={Jul}, pages={356–361} }
 @inproceedings{varma_steer_franzon_2006, title={Developing Improved IO Buffer Behavioral Modeling Methodology Based on IBIS}, ISBN={1424406684}, url={http://dx.doi.org/10.1109/epep.2006.321193}, DOI={10.1109/epep.2006.321193}, abstractNote={A new macromodeling methodology based on IBIS (input/output buffer information specification) models is proposed. IBIS models are known to lack information regarding power and ground bounce (Varma, et. al., 2004 and Yang, et. al., 2005) resulting in incorrect system level simulations. The new macromodel works with available simulators and produces models that can be simulated accurately for simultaneous switching noise (SSN). To demonstrate the solution, a CMOS voltage-mode driver circuit and a MICRON DDR2 driver are simulated using HSPICE and compared with equivalent circuits created with IBIS models of the same drivers}, booktitle={2006 IEEE Electrical Performane of Electronic Packaging}, publisher={IEEE}, author={Varma, Ambrish and Steer, Michael and Franzon, Paul}, year={2006}, month={Oct} }
 @inproceedings{zhang_wilson_bashirullah_franzon_2006, title={Differential current-mode signaling for robust and power efficient on-chip global interconnects}, ISBN={0780392205}, url={http://dx.doi.org/10.1109/epep.2005.1563768}, DOI={10.1109/epep.2005.1563768}, abstractNote={A global interconnect scheme with better current return path control is presented for accurate inductance analysis and robust interconnect design. High performance is obtained by using differential signaling, current-mode sensing, bridge termination, and driver pre-emphasis.}, booktitle={IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005.}, publisher={IEEE}, author={Zhang, Liang and Wilson, J. and Bashirullah, R. and Franzon, P.}, year={2006}, month={Jan} }
 @inproceedings{chandrasekar_wilson_erickson_feng_xu_mick_franzon_2006, title={Fine Pitch Inductively Coupled Connectors for Multi-Gbps Pulse Signaling}, ISBN={1424406684}, url={http://dx.doi.org/10.1109/epep.2006.321178}, DOI={10.1109/epep.2006.321178}, abstractNote={We demonstrate multi-Gbps pulse signaling with 100um diameter coupled inductors across a substrate to substrate interface. This has application in realizing sub-mm pitch surface mount zero insertion force (ZIF) connector interconnect structures}, booktitle={2006 IEEE Electrical Performane of Electronic Packaging}, publisher={IEEE}, author={Chandrasekar, Karthik and Wilson, John and Erickson, Evan and Feng, Zhiping and Xu, Jian and Mick, Stephen and Franzon, Paul}, year={2006}, month={Oct} }
 @inproceedings{wilson_merritt_karaguzel_kang_nagle_grant_pourdeyhemi_franzon_2006, title={High-Frequency Characterization of Printed CPW Lines on Textiles using a Custom Test Fixture}, ISBN={1424404541}, url={http://dx.doi.org/10.1109/spi.2006.289244}, DOI={10.1109/spi.2006.289244}, abstractNote={A screen printer is used to print conductive inks, loaded with silver particles, on nonwoven textiles substrates. To evaluate this technology for use as flexible interconnects; a custom test fixture was designed to assist in the high frequency characterization of CPW transmission lines. Due to the flexible nature of textile substrates it is necessary to have mechanical support at the points of electrical contact. However, the test fixture must not alter the electrical characteristics of the CPW lines. This test fixture removes the electrical effects of the mechanical support, and provides a simple and repeatable methodology for evaluating various types of textiles substrates, conductive inks, geometrical variations, and other parameters. Time-domain reflectometry (TDR) is used to measure the characteristic impedance of samples across geometrical variations in the 10 cm long CPW lines. A comparison showing the effects of the measuring the samples using the test fixture to measuring the samples on a solid acrylic substrate, and a metal plate are presented}, booktitle={2006 IEEE Workship on Signal Propagation on Interconnects}, publisher={IEEE}, author={Wilson, J.M. and Merritt, C. and Karaguzel, B. and Kang, T. and Nagle, H.T. and Grant, E. and Pourdeyhemi, B. and Franzon, P.D.}, year={2006}, month={May} }
 @article{kriplani_nackashi_amsinck_di spigna_steer_franzon_rick_solomon_reimers_2006, title={Physically based molecular device model in a transient circuit simulator}, volume={326}, ISSN={["1873-4421"]}, DOI={10.1016/j.chemphys.2006.03.003}, abstractNote={Abstract Two efficient, physically based models for the real-time simulation of molecular device characteristics of single molecules are developed. These models assume that through-molecule tunnelling creates a steady-state Lorentzian distribution of excess electron density on the molecule and provides for smooth transitions for the electronic degrees of freedom between the tunnelling, molecular-excitation, and charge-hopping transport regimes. They are implemented in the f REEDA™ transient circuit simulator to allow for the full integration of nanoscopic molecular devices in standard packages that simulate entire devices including CMOS circuitry. Methods are presented to estimate the parameters used in the models via either direct experimental measurement or density-functional calculations. The models require 6–8 orders of magnitude less computer time than do full a priori simulations of the properties of molecular components. Consequently, molecular components can be efficiently implemented in circuit simulators. The molecular-component models are tested by comparison with experimental results reported for 1,4-benzenedithiol.}, number={1}, journal={CHEMICAL PHYSICS}, author={Kriplani, Nikhil M. and Nackashi, David P. and Amsinck, Christian J. and Di Spigna, Neil H. and Steer, Michael B. and Franzon, Paul D. and Rick, Ramon L. and Solomon, Gemma C. and Reimers, Jeffrey R.}, year={2006}, month={Jul}, pages={188–196} }
 @inproceedings{xu_wilson_erickson_franzon_2006, title={Pulse Signaling in Inductively Coupled Sockets and Connectors}, booktitle={SRC Student Symposium}, author={Xu, J. and Wilson, J. and Erickson, E. and Franzon, P.}, year={2006}, month={Oct} }
 @inproceedings{kang_merritt_karaguzel_wilson_franzon_pourdeyhimi_grant_nagle_2006, title={Sensors on textile substrates for home-based healthcare monitoring}, ISBN={1-4244-0058-9}, url={http://dx.doi.org/10.1109/ddhh.2006.1624783}, DOI={10.1109/ddhh.2006.1624783}, abstractNote={In this paper we describe progress in developing textile-based sensors for wearable physiological monitoring systems. Active electrodes on nonwoven textile substrates are described for capturing ECG and EOG data. A capacitive sensor for monitoring breathing is presented. Data transmission by coplanar waveguides is also a topic introduced. The future of these devices for home-based healthcare monitoring is considered}, booktitle={Proceedings of the 1st Conference on Distributed Diagnosis and Home Healthcare}, publisher={IEEE}, author={Kang, T-H and Merritt, C. and Karaguzel, B. and Wilson, J. and Franzon, P. and Pourdeyhimi, B. and Grant, E. and Nagle, T.}, year={2006}, pages={5–7} }
 @inproceedings{luo_wilson_xu_mick_franzon_2006, title={Signal integrity and robustness of ACCI packaged systems}, ISBN={0780392205}, url={http://dx.doi.org/10.1109/epep.2005.1563687}, DOI={10.1109/epep.2005.1563687}, abstractNote={AC coupled interconnects (ACCI) enable reliable multiGiga-b/s/channel communication with less than 100/spl mu/m pin pitch, and with BER less than 10/sup -12/. This paper discusses the potential for switching noise, crosstalk and ISI control in ACCI system.}, booktitle={IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005.}, publisher={IEEE}, author={Luo, Lei and Wilson, J. and Xu, Jian and Mick, S. and Franzon, P.}, year={2006}, month={Jan} }
 @inproceedings{oh_franzon_2006, title={TCAM core design in 3D IC for low matchline capacitance and low power}, url={http://dx.doi.org/10.1117/12.695915}, DOI={10.1117/12.695915}, abstractNote={Ternary Content Addressable Memory (TCAM) has been an emerging technology for fast packet forwarding, commonly used in longest prefix match routing. Large table size requirements and wider lookup table data widths have led to higher capacity TCAM designs. However, the fully parallel characteristic of TCAM makes large TCAM design more challenging and limits its capacity due to intensive power consumption. This paper proposes 3D IC technology as a solution to reduce the power consumption by reducing the interconnect capacitances of TCAM. In 3D IC, multiple wafers are stacked on top of each other, and the tiers are vertically connected through 3D vias. 3D vias reduce metal interconnect lengths and parasitic capacitances, resulting in power reduction. In this paper, 3D vias are used to replace matchlines, whose transition during parallel search operations is a major source of high power consumption in TCAM. An analysis of parasitic interconnect capacitance has been done using a quasi-static electromagnetic field simulation tool, Ansoft's Q3D Extractor, on a TCAM memory core in both conventional 2D IC structure and 3D IC structure with the process parameters of the MIT Lincoln Labs 0.18μm FDSOI process. Field analysis and spice simulation results using a capacitance model for interconnects show that a 40% matchline capacitance reduction and a 23% power reduction can be achieved by using a 3-tier 3D IC structure instead of the conventional 2D approach.}, booktitle={Smart Structures, Devices, and Systems III}, publisher={SPIE}, author={Oh, Eun Chu and Franzon, Paul D.}, editor={Al-Sarawi, Said F.Editor}, year={2006}, month={Dec} }
 @inproceedings{xu_wilson_mick_luo_franzon_2005, title={2.8 Gb/s Inductively Coupled Interconnect for 3-D ICs}, booktitle={Japan VLSI Symposium}, author={Xu, J. and Wilson, J. and Mick, S. and Luo, L. and Franzon, P.}, year={2005}, month={Jun} }
 @inproceedings{xu_wilson_mick_luo_2005, title={2.8 Gbps inductively coupled interconnect for 3D ICs}, booktitle={Proceedings of the 2005 symposium on VLSI circuits}, author={Xu, J. and Wilson, J. and Mick, S. and Luo, L.}, year={2005}, month={Jun}, pages={352–355} }
 @inproceedings{luo_wilson_mick_xu_zhang_franzon_2005, title={3Gb/s AC-coupled chip-to-chip communication using a low-swing pulse receiver}, ISBN={0-7803-8904-2}, DOI={10.1109/ISSCC.2005.1494099}, abstractNote={A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.}, booktitle={Proceedings of the 2005 International Solid State Circuits Conference}, author={Luo, L. and Wilson, J.M. and Mick, S.E. and Xu, J. and Zhang, L. and Franzon, P.D.}, year={2005} }
 @article{nath_ghosh_fathelbab_maria_kingon_franzon_steer_2005, title={A tunable combline bandpass filter using Barium Strontium Titanate interdigital varactors on an alumina substrate}, ISBN={["0-7803-8845-3"]}, ISSN={["2576-7216"]}, DOI={10.1109/mwsym.2005.1516670}, abstractNote={Barium strontium titanate (BST) has a field-dependent permittivity that enables it to be used as a dielectric in a voltage-tunable capacitor or varactor. A tunable combline bandpass filter was designed and characterized using BST varactors fabricated on a polycrystalline alumina substrate with copper metallization and is 14 mm /spl times/ 14 mm in size. The center frequency of the filter varies from 1.6 to 2.0 GHz with the application of 200 V tuning voltage. A 25% tuning range was achieved using tuning field strength of 300 kV/cm. The zero bias insertion loss was 6.6 dB and this decreased to 4.3 dB at the high bias state. The return loss was better than 10 dB.}, journal={2005 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM, VOLS 1-4}, publisher={Piscataway, NJ: IEEE}, author={Nath, J and Ghosh, D and Fathelbab, W and Maria, JP and Kingon, AI and Franzon, PD and Steer, MB}, year={2005}, pages={595–598} }
 @article{blum_soto_wilson_brower_pollack_schull_chatterji_lin_johnson_amsinck_et al._2005, title={An Engineered Virus as a Scaffold for Three-Dimensional Self-Assembly on the Nanoscale}, volume={1}, ISSN={1613-6810 1613-6829}, url={http://dx.doi.org/10.1002/smll.200500021}, DOI={10.1002/smll.200500021}, abstractNote={Exquisite control over positioning nanoscale components on a protein scaffold allows bottom-up self-assembly of nanodevices. Using cowpea mosaic virus, modified to express cysteine residues on the capsid exterior, gold nanoparticles were attached to the viral scaffold to produce specific interparticle distances (see picture). The nanoparticles were then interconnected using thiol-terminated conjugated organic molecules that act as "molecular wires", resulting in a 3D spherical conductive network, which is only 30 nm in diameter.}, number={7}, journal={Small}, publisher={Wiley}, author={Blum, Amy Szuchmacher and Soto, Carissa M. and Wilson, Charmaine D. and Brower, Tina L. and Pollack, Steven K. and Schull, Terence L. and Chatterji, Anju and Lin, Tianwei and Johnson, John E. and Amsinck, Christian and et al.}, year={2005}, month={Jul}, pages={702–706} }
 @article{nath_ghosh_maria_kingon_fathelbab_franzon_steer_2005, title={An electronically tunable microstrip bandpass filter using thin-film barium-strontium-titanate (BST) varactors}, volume={53}, ISSN={["1557-9670"]}, DOI={10.1109/TMTT.2005.854196}, abstractNote={A tunable third-order combline bandpass filter using thin-film barium-strontium-titanate varactors and fabricated on a sapphire substrate is reported. Application of 0-200-V bias varied the center frequency of the filter from 2.44 to 2.88 GHz (16% tuning) while achieving a 1-dB bandwidth of 400 MHz. The insertion loss varied from 5.1 dB at zero bias to 3.3 dB at full bias, while the return loss exceeded 13 dB over the range. The third-order intercept of the filter was found to be 41 dBm.}, number={9}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Nath, J and Ghosh, D and Maria, JP and Kingon, AI and Fathelbab, W and Franzon, PD and Steer, MB}, year={2005}, month={Sep}, pages={2707–2712} }
 @inproceedings{wilson_bashirullah_nackashi_winick_franzon_2005, title={An integrated self-masking technique for providing low-loss metallized RF MEMS devices in a polysilicon only MEMS process}, DOI={10.1117/12.607592}, abstractNote={A novel masking technique that enables the complex patterning of metal on any layer of a released MEMS chip is demonstrated. This technique enables a polysilicon only MEMS process to create low-loss RF devices. To illustrate the advantages of post-release metallization, in a polysilicon only MEMS process, a rotating MEMS tunable capacitor that provides a wide and linear tuning range is presented. The core of the design comes from high yield, mechanically proven gear designs from Sandia’s SUMMiT design library. Significant alterations were made to the gear structure to create the final device. Preliminary tests show device capacitance ratios of 1.8:1, with linear tuning. Increased metal deposition to reduce the device air gap, can produce a capacitance ratio over 6:1.}, booktitle={Proceedings of the SPIE Micro Europe}, author={Wilson, J. and Bashirullah, R. and Nackashi, D.P. and Winick, D.A. and Franzon, P.D.}, year={2005} }
 @article{varma_glaser_franzon_2005, title={CAD Flows for Chip-Package CoVerification}, volume={28}, DOI={10.1109/TADVP.2004.841475}, abstractNote={A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package coverification}, number={1}, journal={IEEE Transactions on Advanced Packaging}, author={Varma, A.K. and Glaser, A.W. and Franzon, P.D.}, year={2005}, month={Feb}, pages={194–202} }
 @inbook{franzon_2005, title={Chip-Package Codesign}, booktitle={The Handbook for EDA of Electronic Circuits}, publisher={CRC Press}, author={Franzon, P.}, editor={Scheffer, Lou and Lavagno, Luciano and Martin, GrantEditors}, year={2005} }
 @article{aldwairi_conte_franzon_2005, title={Configurable String Matching Hardware for Speeding Up Intrusion Detection}, volume={33}, ISSN={0163-5964}, url={http://doi.acm.org/10.1145/1055626.1055640}, DOI={10.1145/1055626.1055640}, abstractNote={Signature-based Intrusion Detection Systems (IDSs) monitor network traffic for security threats by scanning packet payloads for attack signatures. IDSs have to run at wire speed and need to be configurable to protect against emerging attacks. In this paper we consider the problem of string matching which is the most computationally intensive task in IDS. A configurable string matching accelerator is developed with the focus on increasing throughput while maintaining the configurability provided by the software IDSs. Our preliminary results suggest that the hardware accelerator offers an overall system performance of up to 14Gbps.}, number={1}, journal={SIGARCH Comput. Archit. News}, author={Aldwairi, Monther and Conte, Thomas and Franzon, Paul}, year={2005}, month={Mar}, pages={99–107} }
 @article{blum_soto_wilson_brower_pollack_schull_chatterji_lin_johnson_amsinck_et al._2005, title={Cover Picture: An Engineered Virus as a Scaffold for Three-Dimensional Self-Assembly on the Nanoscale (Small 7/2005)}, volume={1}, ISSN={1613-6810 1613-6829}, url={http://dx.doi.org/10.1002/smll.200590023}, DOI={10.1002/smll.200590022}, number={7}, journal={Small}, publisher={Wiley}, author={Blum, Amy Szuchmacher and Soto, Carissa M. and Wilson, Charmaine D. and Brower, Tina L. and Pollack, Steven K. and Schull, Terence L. and Chatterji, Anju and Lin, Tianwei and Johnson, John E. and Amsinck, Christian and et al.}, year={2005}, month={Jul}, pages={669–669} }
 @article{blum_soto_wilson_brower_pollack_schull_chatterji_lin_johnson_amsinck_et al._2005, title={Cover Picture: An Engineered Virus as a Scaffold for Three-Dimensional Self-Assembly on the Nanoscale (Small 7/2005)}, volume={1}, ISSN={1613-6810 1613-6829}, url={http://dx.doi.org/10.1002/smll.200590023}, DOI={10.1002/smll.200590023}, number={7}, journal={Small}, publisher={Wiley}, author={Blum, Amy Szuchmacher and Soto, Carissa M. and Wilson, Charmaine D. and Brower, Tina L. and Pollack, Steven K. and Schull, Terence L. and Chatterji, Anju and Lin, Tianwei and Johnson, John E. and Amsinck, Christian and et al.}, year={2005}, month={Jul}, pages={669–669} }
 @article{davis_wilson_mick_xu_hua_mineo_sule_steer_franzon_2005, title={Demystifying 3D ICs: The procs and cons of going vertical}, volume={22}, ISSN={["1558-1918"]}, DOI={10.1109/MDT.2005.136}, abstractNote={This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.}, number={6}, journal={IEEE DESIGN & TEST OF COMPUTERS}, author={Davis, WR and Wilson, J and Mick, S and Xu, M and Hua, H and Mineo, C and Sule, AM and Steer, M and Franzon, PD}, year={2005}, pages={498–510} }
 @inproceedings{xu_grant_kingon_wilson_franzon_2005, title={Drive circuit for a mode conversion rotary ultrasonic motor}, ISBN={0780392523}, url={http://dx.doi.org/10.1109/iecon.2005.1569141}, DOI={10.1109/iecon.2005.1569141}, abstractNote={A mode conversion rotary ultrasonic motor (USM) has potential applications in miniature robotics. However, its electrical drive circuit presents some unique challenges, particularly in producing a high frequency (/spl sim/40 kHz), high voltage (/spl sim/200 V peak-to-peak) signal into a low impedance (/spl sim/100 /spl Omega/) capacitive motor, while achieving high efficiency. This paper describes the design of such a drive circuit, intended for use with a 12 V battery. The drive circuit consists of a switch-mode power converter driving the USM via a step-up planar transformer. Compensation and resonant elements are added to improve the power efficiency. While the peak efficiency of this circuit is 45%, in practice the equivalent impedance of the USM changes with mechanical load and temperature, resulting in an average efficiency of 16%. The admittance vs. frequency characteristic and the equivalent electrical model for a USM prototype are also presented in this paper. The circuit simulations and loaded testing of a full-bridge DC-AC resonant converter with DC-offset module were performed. A load-adapted frequency tracking method has also been proposed to improve the efficiency and stability of the drive circuit.}, booktitle={31st Annual Conference of IEEE Industrial Electronics Society, 2005. IECON 2005.}, publisher={IEEE}, author={Xu, J. and Grant, E. and Kingon, A.I. and Wilson, J.M. and Franzon, P.D.}, year={2005} }
 @inproceedings{zhang_wilson_bashirullah_luo_xu_franzon_2005, title={Driver pre-emphasis techniques for on-chip global buses}, ISBN={1595931376}, url={http://dx.doi.org/10.1145/1077603.1077650}, DOI={10.1145/1077603.1077650}, abstractNote={By using current-sensing differential buses with driver pre-emphasis techniques, power dissipation is reduced by 26.0%-51.2% and peak current is reduced by 63.8%, compared to conventional repeater insertion techniques, for 10mm long buses in TSMC 0.25/spl mu/m technology. This proposed architecture lowers the worst coupling capacitance to total capacitance ratio to 14.4%. It only requires 7.9% more bus routing area than single-ended designs for a 16-bit bus, and saves all of the repeater placement blockages. To further verify that the driver pre-emphasis techniques can also be applied to voltage-mode single-ended buses, a test chip in TSMC 0.18/spl mu/m technology was fabricated and measured.}, booktitle={Proceedings of the 2005 international symposium on Low power electronics and design  - ISLPED '05}, publisher={ACM Press}, author={Zhang, Liang and Wilson, John and Bashirullah, Rizwan and Luo, Lei and Xu, Jian and Franzon, Paul}, year={2005} }
 @article{sonkusale_amsinck_nackashi_di spigna_barlage_johnson_franzon_2005, title={Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process}, volume={28}, ISSN={["1873-1759"]}, DOI={10.1016/j.physe.2005.01.010}, abstractNote={We have demonstrated a new planar edge defined alternate layer (PEDAL) process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by shadow metallization and has the ability to fabricate sub-10 nm nanowires with 20 nm pitch. The process can also be used to make templates for the nano-imprinting with which the crossbar structures can be fabricated. The process involves defining the edge by etching a trench patterned by conventional i-line lithography, followed by deposition of alternating layers of silicon nitride and crystallized a-Si. The thickness of these layers determines the width and spacing of the nanowires. Later the stack is planarized to the edge of the trench by spinning polymer Shipley 1813 and then dry etching the polymer, nitride and polysilicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or polysilicon gives us the array of an aligned nanowires template. After shadow metallization of the required metal, we get metal nanowires on the wafer. The process has the flexibility of routing the nanowires around the logic and memory modules all across the wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques.}, number={2}, journal={PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES}, author={Sonkusale, SR and Amsinck, CJ and Nackashi, DP and Di Spigna, NH and Barlage, D and Johnson, M and Franzon, PD}, year={2005}, month={Jul}, pages={107–114} }
 @inproceedings{sonkusale_amsinck_nackashi_di spigna_barlage_johnson_franzon_2005, title={Fabrication of wafer-scale, aligned Sub-25 nm nanowires and templates using Planar Edge Defined Alternate Layer (PEDAL) Process}, ISBN={0-9767985-2-2}, booktitle={Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show}, author={Sonkusale, S and Amsinck, C.J. and Nackashi, D.P. and Di Spigna, N.H. and Barlage, D and Johnson, M and Franzon, P.D.}, year={2005}, month={May} }
 @inproceedings{dogan_franzon_liu_2005, title={Impact of SOI research Project on microelectronics education: a case study}, ISBN={0-7695-2374-9}, DOI={10.1109/MSE.2005.35}, abstractNote={Microelectronics systems design is a collaborative, multidisciplinary activity, involving the combined efforts of system architects, circuit designers, device engineers, software developers, and process engineers. Semiconductor products are vital to today's $1 trillion/year electronic industry. There is a need for educational programs that prepare engineers for the semiconductor industry. This paper presents the impact of an RF-SoC research project on the career choices of students involved and its broader impact on the microelectronics education in the participating universities. Teaching students the design and test at the physical level is valuable in that it provides the understanding and skills they will need to perform these functions in their subsequent employment.}, booktitle={Proceedings of the IEEE International Conference on Microelectronics systems education}, publisher={IEEE}, author={Dogan, N.S. and Franzon, P. and Liu, W.}, year={2005}, pages={33–34} }
 @inproceedings{chandrasekar_feng_wilson_mick_franzon_2005, title={Inductively Coupled Board-to-Board Connectors}, ISBN={0780389069}, url={http://dx.doi.org/10.1109/ectc.2005.1441411}, DOI={10.1109/ectc.2005.1441411}, abstractNote={This paper discusses the potential application of inductive coupling elements as backplane connectors. Tradeoffs in the choice of inductive elements are discussed and a simple circuit model for electrically large board-to-board transformers is presented. Measured data for a 10mm outer diameter transformer shows an acceptable eye opening for 400Mbps NRZ data, and over 1GHz of bandwidth in the frequency domain. We also discuss how inductive connectors could find application in future long range FR4 backplanes}, booktitle={Proceedings Electronic Components and Technology, 2005. ECTC '05.}, publisher={IEEE}, author={Chandrasekar, K. and Feng, Zhiping and Wilson, J. and Mick, S. and Franzon, P.}, year={2005}, month={Jul}, pages={1109–1113} }
 @inproceedings{damiano_franzon_2005, title={Integrated dynamic body contact for H-gate PD-SOI MOSFETs for high performance/low power}, ISBN={0780384970}, url={http://dx.doi.org/10.1109/soi.2004.1391580}, DOI={10.1109/soi.2004.1391580}, abstractNote={This paper discusses on the integrated dynamic body contact for H-gate PD-SOI MOSFETs for high performance/low power. PD-SOI circuit designers often must explicitly account for the MOSFET body voltage. Here, a dynamic body bias is implemented with a compact layout style to achieve improved performance and reduced power consumption.}, booktitle={2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)}, publisher={IEEE}, author={Damiano, J. and Franzon, P.D.}, year={2005}, month={Mar} }
 @inproceedings{nackashi_amsinck_dispigna_franzon_2005, title={Molecular electronic latches and memories}, DOI={10.1109/nano.2005.1500658}, abstractNote={Many two terminal molecular devices functioning as diodes have been synthesized with responses similar to solid state devices such as rectifying and resonant tunneling diodes. In this paper, the feasibility of integrating these molecular diodes into current circuit architectures is explored. A bistable latch and memory architecture are simulated using IV data from the 2'-amino-4-ethynylphenyl-4'-ethynylphenyl-5'-nitro-1-bensenethiolate molecule previously published by the Reed group at Yale University. HSPICE simulation results are used to illustrate the performance of a bistable latch and a memory array.}, booktitle={IEEE Nano}, author={Nackashi, D.P. and Amsinck, C.J. and DiSPigna, N.H. and Franzon, P.D.}, year={2005}, month={Jul}, pages={819–822} }
 @inproceedings{franzon_nackashi_dispigna_sonkusale_2005, title={Molecular electronics – devices and circuits technology}, booktitle={Proceedings IFIP VLSI-SoC 2005}, author={Franzon, P. and Nackashi, D. and DiSpigna, N. and Sonkusale, S.}, year={2005}, pages={57–63} }
 @article{mehrotra_rao_conte_franzon_2005, title={Optimal chip-package codesign for high-performance DSP}, volume={28}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2005.846937}, abstractNote={In high-performance DSP systems, the memory bandwidth can be improved using high-density interconnect technology and appropriate memory mapping. High-density MCM and flip-chip solder bump technology is used to achieve a system with an I/O bandwidth of 100 Gb/s/cm2 die. The use of DRAMs in these systems usually make the performance of these systems poor, and some algorithms make it difficult to fully utilize the available memory bandwidth. This paper presents the design of a fast Fourier transform (FFT) engine that gives SRAM-like performance in a DRAM-based system. It uses almost 100% of the available burst-mode memory bandwidth. This FFT engine can compute a million-point FFT in 1.31 ms at a sustained computation rate of 8.64 /spl times/ 10/sup 10/ floating-point operations per second (FLOPS). This is at least an order of magnitude better than conventional systems.}, number={2}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Mehrotra, P and Rao, V and Conte, TM and Franzon, PD}, year={2005}, month={May}, pages={288–297} }
 @article{amsinck_di spigna_nackashi_franzon_2005, title={Scaling constraints in nanoelectronic random-access memories}, volume={16}, ISSN={["1361-6528"]}, DOI={10.1088/0957-4484/16/10/047}, abstractNote={Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F2) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 × 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 × 512.}, number={10}, journal={NANOTECHNOLOGY}, author={Amsinck, CJ and Di Spigna, NH and Nackashi, DP and Franzon, PD}, year={2005}, month={Oct}, pages={2251–2260} }
 @article{scheffler_franzon_troster_2004, title={A "Defect level versus cost" system tradeoff for electronics manufacturing}, volume={27}, ISSN={["1521-334X"]}, DOI={10.1109/TEPM.2004.830513}, abstractNote={Both cost and quality are important features when manufacturing today's high-performance electronics. Unfortunately, the two design goals (low) cost and (high) quality are somewhat mutually exclusive. High testing effort (and thus, quality) comes with a considerable cost, and lowering test activities has significant impact on the delivered quality. In this paper, we present a new structured search method to obtain the best combination of these two goals. It features a Petri-net oriented cost/quality modeling approach and uses a Pareto chart to visualize the results. The search for the Pareto-optimal points is done by means of a genetic algorithm. With our method, we optimize a manufacturing process for a global positioning system (GPS) front end. The optimized process clearly outperformed the standard fabrication process.}, number={1}, journal={IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING}, author={Scheffler, M and Franzon, PD and Troster, G}, year={2004}, month={Jan}, pages={67–76} }
 @inproceedings{yadav_hamilton_sears_viniotis_conte_franzon_2004, title={A configurable classification engine for polymorphous chip architecture}, booktitle={Proceedings of the ACM BEACON Workshop}, author={Yadav, M. and Hamilton, P. and Sears, R. and Viniotis, Y. and Conte, T. and Franzon, P.D.}, year={2004} }
 @article{xu_mick_wilson_luo_chandrasekar_erickson_franzon_2004, title={AC coupled interconnect for dense 3-D ICs}, volume={51}, ISSN={["1558-1578"]}, DOI={10.1109/TNS.2004.834712}, abstractNote={This paper presents the potential application of AC coupled interconnect (ACCI) for dense three-dimensional (3-D) integrated circuits (ICs). The concept of inductive ACCI for 3-D ICs has been proposed. Combined with the "through vias" technology, inductive ACCI can provide small pitch vertical interconnects, as well as an excellent thermal solution for dense 3-D ICs. Transformer modeling and transceiver circuit design have also been investigated. Simulations predict that, for 20 /spl mu/m thinned die stacks coupled by a 100 /spl mu/m diameter transformer, the transceiver circuit fed with a 5 Gbps data stream consumes 14.5 mW power.}, number={5}, journal={IEEE TRANSACTIONS ON NUCLEAR SCIENCE}, author={Xu, J and Mick, S and Wilson, J and Luo, L and Chandrasekar, K and Erickson, E and Franzon, PD}, year={2004}, month={Oct}, pages={2156–2160} }
 @article{mick_luo_wilson_franzon_2004, title={Buried bump and AC coupled interconnection technology}, volume={27}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2004.825482}, abstractNote={A novel physical structure, buried solder bumps, is introduced that solves the compliance problems that exist in scaling present area array technologies to ever-higher densities. In this technique, buried bumps provide dc connections between integrated circuits and substrates and ac coupled interconnections provide paths for ac signals across the same interface. This approach requires co-design of packaging and circuits and meets the growing demands for both interconnect density and bandwidth. AC coupled interconnection arrays can be built with pitches for ac signals below 100 /spl mu/m and data rates of 6 Gb/s per I/O. This paper presents the physical and circuit aspects of this work as well as measured results from capacitively-coupled circuits fabricated in Taiwan semiconductor manufacturing Company (TSMC) 0.35-/spl mu/m technology. Simulated results from capacitively-coupled circuits in TSMC 0.18 /spl mu/m are also presented.}, number={1}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Mick, S and Luo, L and Wilson, J and Franzon, P}, year={2004}, month={Feb}, pages={121–125} }
 @article{mohan_choi_mick_hart_chandrasekar_cangellaris_franzon_steer_2004, title={Causal reduced-order modeling of distributed structures in a transient circuit simulator}, volume={52}, ISSN={["1557-9670"]}, DOI={10.1109/TMTT.2004.834588}, abstractNote={Fosters' canonical representation of the transfer characteristic of a linear system is the key to causal fully convergent incorporation of distributed structures in transient circuit simulators. The implementation of the Foster's model in the fREEDA circuit simulator is reported and the modeling of a two-port coupled inductor is presented as an example.}, number={9}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Mohan, R and Choi, MJ and Mick, SE and Hart, FP and Chandrasekar, K and Cangellaris, AC and Franzon, PD and Steer, MB}, year={2004}, month={Sep}, pages={2207–2214} }
 @article{schaffer_glaser_franzon_2004, title={Chip-package co-implementation of a triple DES processor}, volume={27}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2004.824944}, abstractNote={This paper describes the design and implementation of a dedicated data encryption standard (DES) processor. The processor consists of three 0.6 /spl mu/m complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) mounted on a single MCM-D thin-film substrate. Each chip can operate on an individual data stream, or the three can be cascaded to implement the so-called "triple-DES" (3DES) function for increased security. Measurements show 3DES operation at 110 MHz, which translates to a throughput of over 7 Gb/s, the highest reported 3DES throughput to date. System features which contribute to this throughput are the use of area-array (flip-chip) input/output (I/O) and global IC power/ground/clock distribution in the MCM package. In this case, package-level distribution reduced clock skew by 150 ps, and reduced the chip area required for power distribution by 20%. This paper also includes measurements of switching noise of the MCM's V/sub dd/ plane and how it correlates with a simple model of the system power distribution.}, number={1}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Schaffer, T and Glaser, A and Franzon, PD}, year={2004}, month={Feb}, pages={194–202} }
 @article{seminario_ma_agapito_yan_araujo_bingi_vadlamani_chagarlamudi_sudarshan_myrick_et al._2004, title={Clustering effects on discontinuous gold film NanoCells}, volume={4}, ISSN={["1533-4899"]}, DOI={10.1166/jnn.2004.104}, abstractNote={Reproducible negative differential resistance (NDR)-like switching behavior is observed in NanoCells. This behavior is attributed to the formation of filaments and clusters between the discontinuous gold films. Control experiments are performed by self-assembly of insulating molecules between the gold islands and conducting molecules on these islands. Additional control experiments are performed by removing the filaments and clusters between islands using a piranha bath. The results are consistent with theoretical predictions and extend the domain of molecular electronics based in organic molecules to include nanosized clusters as active units. This facilitates a scenario where synthetically accessible organic molecules, with defined characteristics, can be adjusted by metallic nanoclusters as an in situ fine-tuning element, able to compensate for the lack of addressing in the nanosize regime.}, number={7}, journal={JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY}, author={Seminario, JM and Ma, YF and Agapito, LA and Yan, LM and Araujo, RA and Bingi, S and Vadlamani, NS and Chagarlamudi, K and Sudarshan, TS and Myrick, ML and et al.}, year={2004}, month={Sep}, pages={907–917} }
 @inproceedings{aldwairi_conte_franzon_2004, title={Configureable String matching hardware for speeding up intrusion detection}, booktitle={ACM Workshop on secure networking}, author={Aldwairi, M. and Conte, T. and Franzon, P.}, year={2004}, month={Oct} }
 @inproceedings{franzon_amsinck_di spigna_sonkusale_nackashi_2004, title={Integration for Molecular Electronics}, booktitle={Proceedings of the Conference on Foundations of NanoScience}, author={Franzon, P. and Amsinck, C. and Di Spigna, N. and Sonkusale, Sachin and Nackashi, D.}, year={2004}, month={Apr} }
 @inproceedings{varma_steer_franzon_2004, title={SSN issues with IBIS models}, ISBN={0-7803-8667-1}, DOI={10.1109/EPEP.2004.1407554}, abstractNote={A CMOS driver circuit is simulated in HSPICE and compared with an equivalent circuit created with IBIS (input/output buffer information specification) models of the same drivers. The IBIS models are created using the s2ibis tool from North Carolina State University. IBIS model of the driver is also compared against model created using spline functions with finite time difference approximation modeling techniques. The three modeling techniques are analyzed for accuracy in modeling simultaneous switching noise in drivers.}, booktitle={Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Varma, A. and Steer, M. and Franzon, P.}, year={2004}, month={Oct}, pages={87–90} }
 @inproceedings{zhang_liu_bashirullah_wilson_franzon_2004, title={Simplified delay design guidelines for on-chip global interconnects}, author={Zhang, L. and Liu, W. and Bashirullah, R. and Wilson, J. and Franzon, P.}, year={2004}, month={Apr}, pages={29–32} }
 @inproceedings{varma_lipa_glaser_steer_franzon_2004, title={Simultaneous switching noise in IBIS models}, volume={3}, ISBN={0-7803-8443-1}, DOI={10.1109/ISEMC.2004.1349963}, abstractNote={In this paper, a tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model. A CMOS driver circuit is simulated in HSPICE and compared with an equivalent circuit created with IBIS models of the same drivers. Outputs from the drivers are compared IBIS models are also compared against macro-models of nonlinear digital drivers using spline functions with finite time difference approximation modeling techniques.}, booktitle={Proceedings of the 2004 International Symposium on Electromagnetic Compatibility (IEEE Cat. No.04CH37559)}, publisher={IEEE}, author={Varma, A. and Lipa, S. and Glaser, A. and Steer, M. and Franzon, P.}, year={2004}, month={Aug}, pages={1000–1004} }
 @inproceedings{palmer_mulling_dessent_grant_eischen_gruverman_kingon_franzon_2004, title={The Design, Fabrication and Characterization of Millimeter Scale Motors for Miniature Direct Drive Robots}, ISBN={0-7803-8232-3}, ISSN={1050-4729}, url={http://dx.doi.org/10.1109/robot.2004.1302454}, DOI={10.1109/ROBOT.2004.1302454}, abstractNote={This paper reports on research into miniature, direct drive, high force/torque motors to support insect-sized mobile robotic platforms. The primary focus is on scalable motors based on piezoelectric transducers. The contributions of this work include: (1) the design, analysis, and characterization of a miniature mode conversion rotary ultrasonic motor based on a piezoelectric stack transducer; this produced a static torque density of 0.37 Nm/kg, (2) a millimeter scale linear piezometer, constructed with a parallel arrangement of annular stressed unimorph piezoelectric transducers and passive latches, exhibited 0.23 N of blocked force, and (3) simulation data is presented that compares these motor concepts to commercial systems in the context of scalability. Results suggest that smaller versions of the rotary ultrasonic motor would possess a static torque density seven times that of a commercial 3-mm electromagnetic system. This technology shows promise for driving the platform.}, booktitle={Proceedings of the IEEE International Conference on Robotics and Automation ’04}, publisher={IEEE}, author={Palmer, J.A. and Mulling, J.F. and Dessent, B. and Grant, E. and Eischen, J.W. and Gruverman, A. and Kingon, A. and Franzon, P.D.}, year={2004}, month={Apr}, pages={4668–4673} }
 @article{palmer_dessent_mulling_usher_grant_eischen_kingon_franzon_2004, title={The design and characterization of a novel piezoelectric transducer-based linear motor}, volume={9}, ISSN={["1941-014X"]}, DOI={10.1109/TMECH.2004.828647}, abstractNote={Before microminiature robots can be realized, new direct drive micromotor systems must be developed. In this research, a linear motor system for a miniature jumping robot was desired. However, current systems must display better force/torque characteristics than is currently available. This paper deals with the design, construction, and testing, of a macro-scale, unidirectional, direct drive linear piezomotor that operates like an inchworm. It uses a parallel arrangement of unimorph piezoelectric transducers, in conjunction with passive mechanical latches, to perform work on a coil spring. Experimental results showed that the linear piezomotor achieved a maximum no-load velocity of 161 mm/s, and a blocked force of 14 N, at a drive signal frequency of 100 Hz. Thereafter, back slip in the latch assembly restricted the forward motion. Based on the results obtained with the macro-level linear piezomotor, it is concluded that smaller direct drive piezomotor designs based on unimorph piezoelectric transducers are achievable. System scalability will be addressed in a future publication.}, number={2}, journal={IEEE-ASME TRANSACTIONS ON MECHATRONICS}, author={Palmer, JA and Dessent, B and Mulling, JF and Usher, T and Grant, E and Eischen, JW and Kingon, AI and Franzon, PD}, year={2004}, month={Jun}, pages={392–398} }
 @inproceedings{yuce_liu_bharat_damaino_franzon_2004, title={The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers}, ISBN={0-7803-8495-4}, DOI={10.1109/CICC.2004.1358893}, abstractNote={A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-/spl mu/m silicon on insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 /spl mu/W.}, booktitle={Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)}, publisher={IEEE}, author={Yuce, M.R. and Liu, W. and Bharat, B. and Damaino, J. and Franzon, P.D.}, year={2004}, pages={591–594} }
 @inproceedings{yuce_liu_damiano_bharat_franzon_nugan_2003, title={A low power PSK receiver for space applications in 0.35 µm CMOS}, ISBN={0-7803-7842-3}, DOI={10.1109/CICC.2003.1249381}, abstractNote={An all-digital and low power PSK baseband receiver circuit using silicon on insulator technology (SOI) is designed for space applications. The receiver employs double differential detection to improve the receiver's robustness to Doppler effect as well as a 1 bit A/D at the front to reduce complexity and power. Operating at a UHF frequency (435 MHz), the receiver supports a wide range of data rates (0.1-100 kb/s). From test results, the power consumption of the baseband circuit, including the 1 bit A/D converter is below 1 mW for data rates up to 100 kb/s.}, booktitle={Proceedings of the IEEE Custom Integrated Circuits Conference}, publisher={IEEE}, author={Yuce, M.R. and Liu, W. and Damiano, J. and Bharat, B. and Franzon, P.D. and Nugan, N.S.}, year={2003}, month={Sep}, pages={155–158} }
 @inproceedings{xu_mick_wilson_luo_chandrasakhar_franzon_2003, place={Seattle, Washington}, title={AC Coupled Interconnect for Dense 3-D Systems}, ISBN={0-7803-8257-9}, ISSN={1082-3654}, DOI={10.1109/NSSMIC.2003.1352013}, abstractNote={This paper presents the potential application of AC Coupled Interconnect (ACCI) for dense three-dimensional (3-D) ICs. The concept of inductive ACCT for 3-D stacking ICs has been proposed. Combined with the "through vias" technology, the inductive ACCI can provide small pitch vertical interconnects, as well as an excellent thermal solution for dense 3-D ICs. The transformer modeling and transceiver circuit design have also been investigated. The simulations predict that for 20 /spl mu/m thinned die stacks coupled by a 100 /spl mu/m diameter transformer, the transceiver circuit fed with a 5 Gbps input stream consumes 15.6 mW power.}, booktitle={Proceedings of the IEEE Conference on Nuclear Science and Imaging}, publisher={IEEE}, author={Xu, Jian and Mick, Stephen and Wilson, John and Luo, Lei and Chandrasakhar, Karthik and Franzon, Paul}, year={2003}, month={Oct} }
 @inproceedings{franzon_mick_wilson_luo_chandrasakhar_2003, title={AC Coupled Interconnect for High-Density High-Bandwidth Packaging}, url={http://dx.doi.org/10.7567/ssdm.2003.g-6-1}, DOI={10.7567/ssdm.2003.g-6-1}, abstractNote={AC Coupled Interconnection (ACCI), in conjunction with buried solder bump technology, provides a method to achieve signal I/O pitches of less than 100 μm and signaling rates greater than 3 Gbps per I/O on integrated circuits, while preserving excellent signal integrity. This paper presents a summary of approaches and status capacitive and inductive versions of AC Coupled Interconnect Systems.}, booktitle={Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials}, publisher={The Japan Society of Applied Physics}, author={Franzon, Paul and Mick, Stephen and Wilson, John and Luo, Lei and Chandrasakhar, Karthik}, year={2003}, pages={67–69} }
 @inproceedings{varma_glaser_franzon_2003, title={CAD flows for chip-package codesign}, ISBN={0-7803-8128-9}, DOI={10.1109/EPEP.2003.1249989}, abstractNote={A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.}, booktitle={Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Varma, A. and Glaser, A. and Franzon, P.}, year={2003}, month={Oct}, pages={11–14} }
 @inproceedings{franzon_kingon_mick_wilson_luo_chandrasakhar_xu_bonafede_huffman_statler_et al._2003, title={High Frequency, High Density Interconnect Using AC Coupling}, DOI={10.1557/PROC-783-B6.1}, abstractNote={ABSTRACT}, booktitle={Fall MRS Conference}, author={Franzon, Paul and Kingon, Angus and Mick, Stephen and Wilson, John and Luo, Lei and Chandrasakhar, Karthik and Xu, Jian and Bonafede, Salvatore and Huffman, Alan and Statler, Chad and et al.}, year={2003}, month={Dec} }
 @article{stan_franzon_goldstein_lach_ziegler_2003, title={Molecular electronics: From devices and interconnect to circuits and architecture}, volume={91}, ISSN={["1558-2256"]}, DOI={10.1109/JPROC.2003.818327}, abstractNote={As the dominating CMOS technology is fast approaching a "brick wall," new opportunities arise for competing solutions. Nanoelectronics has achieved several breakthroughs lately and promises to overcome many of the limitations intrinsic to current semiconductor approaches. Most of the results in this area reported until now focus on devices and interconnect; this work goes several steps further and presents issues related to circuits and architecture. Based on proposed nanoscale interconnect and device structures, we explore the design space available to the nanoelectronic circuit designer and system architect.}, number={11}, journal={PROCEEDINGS OF THE IEEE}, author={Stan, MR and Franzon, PD and Goldstein, SC and Lach, JC and Ziegler, MM}, year={2003}, month={Nov}, pages={1940–1957} }
 @article{tour_cheng_nackashi_yao_flatt_st angelo_mallouk_franzon_2003, title={NanoCell electronic memories}, volume={125}, ISSN={["1520-5126"]}, DOI={10.1021/ja036369g}, abstractNote={NanoCells are disordered arrays of metallic islands that are interlinked with molecules between micrometer-sized metallic input/output leads. In the past, simulations had been conducted showing that the NanoCells may function as both memory and logic devices that are programmable postfabrication. Reported here is the first assembly of a NanoCell with disordered arrays of molecules and Au islands. The assembled NanoCells exhibit reproducible switching behavior and two types of memory effects at room temperature. The switch-type memory is characteristic of a destructive read, while the conductivity-type memory features a nondestructive read. Both types of memory effects are stable for more than a week at room temperature, and bit level ratios (0:1) of the conductivity-type memory have been observed to be as high as 10(4):1 and reaching 10(6):1 upon ozone treatment, which likely destroys extraneous leakage pathways. Both molecular electronic and nanofilamentary metal switching mechanisms have been considered, though the evidence points more strongly toward the latter. The approach here demonstrates the efficacy of a disordered nanoscale array for high-yielding switching and memory while mitigating the arduous task of nanoscale patterning.}, number={43}, journal={JOURNAL OF THE AMERICAN CHEMICAL SOCIETY}, author={Tour, JM and Cheng, L and Nackashi, DP and Yao, YX and Flatt, AK and St Angelo, SK and Mallouk, TE and Franzon, PD}, year={2003}, month={Oct}, pages={13279–13283} }
 @inproceedings{varma_glaser_lipa_steer_franzon_2003, title={The development of a macro-modeling tool to develop IBIS models}, ISBN={0-7803-8128-9}, DOI={10.1109/EPEP.2003.1250049}, abstractNote={A tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented. This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model.}, booktitle={Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Varma, A. and Glaser, A. and Lipa, S. and Steer, M. and Franzon, P.}, year={2003}, month={Oct}, pages={177–280} }
 @inproceedings{mick_wilson_franzon_2002, title={4 Gbps AC Coupled Interconnection}, ISBN={0-7803-7250-6}, DOI={10.1109/CICC.2002.1012783}, abstractNote={AC coupled interconnects enable multi-gigabit-persecond communication data rates between integrated circuits with very high pin counts and low power consumption. AC coupling can be realized with either series capacitive or inductive coupling elements. Capacitive AC coupling offers better performance when low power I/O buffers are required and when there is sufficient area to dedicate to coupling capacitors in the top-level metal of each IC. At a slight expense of circuit complexity, inductive AC coupling can be used to bring I/O pad pitches down to 75 /spl mu/m and maintain a controlled impedance connection. A novel physical structure, buried solder bumps, are used as a solution for providing DC power and ground connections across the same surface as the AC connections. When used in conjunction with NRZ-tolerant receivers, and current-mode signaling, highly effective interconnect structures can be built. As well as presenting both physical and circuit aspects of this work, experimental results are shown.}, booktitle={Proceedings of the IEEE Custom Integrated Circuits Conference}, publisher={IEEE}, author={Mick, S.E. and Wilson, J.M. and Franzon, P.}, year={2002}, pages={133–140} }
 @inproceedings{mehortra_franzon_2002, title={Binary Search Schemes for Fast IP Lookups}, ISBN={0-7803-7632-3}, DOI={10.1109/GLOCOM.2002.1188551}, abstractNote={Route lookup is becoming a very challenging problem due to the increasing size of routing tables. To determine the outgoing port for a given address, the longest matching prefix among all the prefixes, needs to be determined. This makes the task of searching in a large database quite difficult. Our paper describes binary search schemes that allow fast address lookups. Binary search can be performed on the number of entries or on the number of mutually disjoint prefixes. Lookups can be performed in O(N) time, where N is number of entries and the amount of memory required to store the binary database is also O(N). These schemes scale very well with both large databases and for longer addresses (as in IPv6).}, booktitle={Proceedings of the IEEE Globecom}, publisher={IEEE}, author={Mehortra, P. and Franzon, P.}, year={2002}, month={Nov}, pages={2005–2009} }
 @inproceedings{mick_luo_wilson_franzon_2002, title={Buried solder bump connections for high- density capacitive coupling}, ISBN={0-7803-7451-7}, DOI={10.1109/EPEP.2002.1057916}, abstractNote={AC coupled interconnects enable reliable, multi-gigabit-per-second communication data rates between integrated circuits with very high pin counts and low power consumption. When used in conjunction with NRZ-tolerant receivers, interconnect arrays with pitches below 100 /spl mu/m and data rates of 6 Gbps/per pin can be built.}, booktitle={Proceedings of the IEEE Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Mick, S. and Luo, L. and Wilson, J. and Franzon, P.}, year={2002}, month={Oct}, pages={205–208} }
 @inproceedings{basel_steer_franzon_2002, title={Hierarchical simulation of high speed digital interconnects using a packaging simulator}, ISBN={0780309146}, url={http://dx.doi.org/10.1109/ectc.1994.367647}, DOI={10.1109/ectc.1994.367647}, abstractNote={A hierarchical strategy is presented which permits the tradeoff of modeling and simulation accuracy with simulation speed in the simulation of high speed signals on interconnects in multichip modules and printed circuit boards. Using a point modeling paradigm for discontinuities and impulse response thresholding a smooth transition is achieved between delay modeling and full circuit simulation.<<ETX>>}, booktitle={1994 Proceedings. 44th Electronic Components and Technology Conference}, publisher={IEEE}, author={Basel, M.S. and Steer, M.B. and Franzon, P.D.}, year={2002}, month={Dec} }
 @inproceedings{nakkar_franzon_2002, title={Low power logical element for FPGA fabric}, ISBN={0-7803-7573-4}, DOI={10.1109/ICM-02.2002.1161495}, abstractNote={Logical Element (LE) is the basic building block of FPGA fabric or any re-configurable computing machines. Logical Element basically consists of look-up tables according to A.B. Smith et al. (2000). This paper shows a low power LE. The low power is achieved by taking advantage of the commutative property of operations. This property will allow the data to be reorganized such that there will be separate paths for logic state 0 and logic state 1. The approach is targeted to reduce switching activity when possible. This paper shows 28% increase in power savings.}, booktitle={Proceedings of the IEEE International Conference on Microelectronics}, publisher={IEEE}, author={Nakkar, M. and Franzon, P.}, year={2002}, month={Dec}, pages={55–57} }
 @article{tour_van zandt_husband_husband_wilson_franzon_nackashi_2002, title={Nanocell logic gates for molecular computing}, volume={1}, ISSN={["1536-125X"]}, DOI={10.1109/TNANO.2002.804744}, abstractNote={Molecular electronics seeks to build electrical devices to implement computation - logic and memory - using individual or small collections of molecules. These devices have the potential to reduce device size and fabrication costs, by several orders of magnitude, relative to conventional CMOS. However, the construction of a practical molecular computer will require the molecular switches and their related interconnect technologies to behave as large-scale diverse logic, with input/output wires scaled to molecular dimensions. It is unclear whether it is necessary or even. possible to control the precise regular placement and interconnection of these diminutive molecular systems. This paper describes genetic algorithm-based simulations of molecular device structures in a nanocell where placement and connectivity of the internal molecular switches are not specifically directed and the internal topology is generally disordered. With some simplifying assumptions, these results show that it is possible to use easily fabricated nanocells as logic devices by setting the internal molecular switch states after the topological molecular assembly is complete. Simulated logic devices include an inverter, a NAND gate, an XOR gate and a 1-bit adder. Issues of defect and fault tolerance are addressed.}, number={2}, journal={IEEE TRANSACTIONS ON NANOTECHNOLOGY}, author={Tour, JM and Van Zandt, WL and Husband, CP and Husband, SM and Wilson, LS and Franzon, PD and Nackashi, DP}, year={2002}, month={Jun}, pages={100–109} }
 @inproceedings{mehrotra_baldine_stevenson_franzon_2002, title={Network Processor Design for Optical Burst Switched Networks}, ISBN={0-7803-6741-3}, DOI={10.1109/ASIC.2001.954715}, abstractNote={Scalable hardware, architectures are required for optical burst switched (OBS) networks where future fibers may be handling 4Tbps or more. Issues investigated include centralized vs. distributed architectures, sealing issues related to performance, and the hardware impact of just-in-time (JIT) vs. just-enough-time (JET) signaling.}, booktitle={Proceedings of the 14th Annual IEEE International ASIC/SOC Conference}, publisher={IEEE}, author={Mehrotra, P. and Baldine, I. and Stevenson, D. and Franzon, P.}, year={2002}, pages={296–300} }
 @inproceedings{mehortra_franzon_2002, title={Novel Hardware Implementation for Fast Address Lookups}, ISBN={4-88552-184-X}, DOI={10.1109/HPSR.2002.1024217}, abstractNote={The most time critical part in packet forwarding is the route lookup which determines the next hop address of the packet. The problem of searching for routes in large databases is compounded by the fact that routing tables store variable length prefixes and their corresponding next hop addresses. In order to forward a packet, routers need to find the longest matching prefix for the destination address. The work presented describes a new fast and efficient algorithm for searching a large database. The scheme described requires several accesses to a small, fast on-chip SRAM and only one access to a slower DRAM in order to determine the next hop address. The paper discusses some of the related work and approaches in performing route lookups. It describes the proposed algorithm where only a single off-chip DRAM access is required to determine the next hop address. It discusses some of the details of the hardware implementation and lists some of the results of the scheme. Some of the design issues are also discussed.}, booktitle={Proceedings of 2002 Workshop on High Performance Switching and Routing}, publisher={IEEE}, author={Mehortra, P. and Franzon, P.}, year={2002} }
 @article{mehrotra_franzon_2002, title={Novel hardware architecture for fast address lookups}, volume={40}, ISSN={0163-6804}, url={http://dx.doi.org/10.1109/mcom.2002.1046995}, DOI={10.1109/mcom.2002.1046995}, abstractNote={For every packet an IP router receives, it makes a routing decision based on the packet's destination address. The router's forwarding rate is usually limited by the rate at which it can make these decisions. We describe a new method for implementing route lookups in hardware. Our method can be implemented in the forwarding engine of a network processor or router using a small on-chip SRAM and an off-chip DRAM, and it achieves a rate of one lookup per DRAM random access time. We present our method and discuss an implementation that uses a DRAM with 64 ns random access time to give over 15 million lookups per second. Our tests show that the method performs well for realistic routing tables while using only modest amounts of memory.}, number={11}, journal={IEEE Communications Magazine}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Mehrotra, P. and Franzon, P.D.}, year={2002}, month={Nov}, pages={66–71} }
 @inproceedings{mick_franzon_huffman_2002, title={Packaging Technology for AC Coupled Interconnection}, booktitle={IMAPS Flip-Chip Conference}, author={Mick, S. and Franzon, P. and Huffman, A.}, year={2002}, month={Jul} }
 @inproceedings{franzon_amsinck_nackashi_despagna_2002, title={Scalable Molecular Circuit Architectures}, booktitle={2002 Engineering Foundation Conference on Molecular Computing}, author={Franzon, P. and Amsinck, C.J. and Nackashi, D.P. and DeSpagna, N.}, year={2002}, month={Dec} }
 @article{meshel_nackashi_franzon_sheetz_2002, title={Single force measurements on 3D collagen matrix}, volume={82}, number={1}, journal={Biophysical Journal}, author={Meshel, A.S. and Nackashi, D.P. and Franzon, P.D. and Sheetz, M.P.}, year={2002}, month={Jan} }
 @inproceedings{wilson_bashirullah_nackashi_winick_duewer_franzon_2001, title={Design of rotating MEMS tunable capacitors for use at RF and Microwave frequencies}, booktitle={Proceedings of the SPIE International Symposium on Microelectronics and MEMS}, author={Wilson, John and Bashirullah, Rizwan and Nackashi, David and Winick, David and Duewer, Bruce and Franzon, Paul D.}, year={2001}, month={Dec} }
 @inproceedings{duewer_winick_oberhofer_muth_franzon_2001, title={Improving Interconnect Characteristics of Thin Film MEMS Processes}, booktitle={Proceedings of the SPIE International Symposium on Microelectronics and MEMS}, author={Duewer, B. and Winick, D. and Oberhofer, A. and Muth, J. and Franzon, P.}, year={2001}, month={Dec} }
 @article{mulling_usher_dessent_palmer_franzon_grant_kingon_2001, title={Load characterization of high displacement piezoelectric actuators with various end conditions}, volume={94}, ISSN={["0924-4247"]}, DOI={10.1016/S0924-4247(01)00688-4}, abstractNote={Piezoelectric ceramic transducers are characterized by relatively small strains on the order of 0.1%. One method of achieving significantly larger displacements is to utilize flexural mode actuators, such as unimorphs or bimorphs. In this paper, we investigate a particular type of stressed unimorph flexural actuator, viz. the ‘THUNDER’ actuators. (THUNDER™ is a trademark of Face International Corporation). These stressed unimorphs are of interest due to their particularly large flexural strains. To determine their versatility as high displacement actuators, it was necessary to investigate their actuation capability as a function of load. In addition, our investigation determined that end conditions have an appreciable effect, which has also not been reported in the literature. Therefore, experimental results of the load capabilities of these high displacement actuators with various end conditions are presented here. Commercially available rectangular actuators were chosen for this study. The actuators had been constructed by bonding thin PZT ceramics (0.152 mm thick, 1.37 cm wide, 3.81 cm long) to stainless steel sheets (0.20 mm thick, 1.27 cm wide, 6.35 cm long). They were operated in a flexural mode. It was shown that progressively restrictive end conditions increased the stiffness, ranging from 2.5 to 23 N/m, enhancing the load capabilities of the actuator. In some cases, displacement actually increased as a function of load. This enhanced stiffness was obtained at a cost of reduced no load flexural strain (defined as the ratio of flexural displacement and ceramic length), ranging from 1.08% for free-end conditions to 0.2% for highly restricted end conditions. The load bearing capabilities were tested out to 10 N for most end conditions.}, number={1-2}, journal={SENSORS AND ACTUATORS A-PHYSICAL}, author={Mulling, J and Usher, T and Dessent, B and Palmer, J and Franzon, P and Grant, E and Kingon, A}, year={2001}, month={Oct}, pages={19–24} }
 @inproceedings{wood_lipa_franzon_steer_2001, title={Multi-gigahertz low-power low-skew rotary clock scheme}, booktitle={Proceedings International Conference On Solid State Circuits}, author={Wood, J. and Lipa, S. and Franzon, P. and Steer, M.}, year={2001}, pages={400–401, 470} }
 @inproceedings{gahide_hodge_seyam_oxenham_franzon_2001, title={Smart sensors to monitor warp tension and breaks on a loom}, number={2001}, author={Gahide, S. and Hodge, G. and Seyam, A. and Oxenham, W. and Franzon, P.}, year={2001} }
 @inproceedings{franzon_2001, title={The Future of Molecular Electronics}, booktitle={Proceedings of the International Conference on Computer Aided Design of Integrated Circuits}, author={Franzon, P.}, year={2001} }
 @inproceedings{gahide_seyam_hodge_oxenham_franzon_2000, title={Application of micromachines to textiles: Using smart sensors to monitor warp tension and breaks during formation of woven fabrics}, booktitle={Proceedings of the International Mechanical Engineering Congress & Exposition, ASME, Orlando (FL), November 2000}, publisher={New York: ASME}, author={Gahide, S. and Seyam, A. and Hodge, G. and Oxenham, W. and Franzon, P.}, year={2000} }
 @inproceedings{mulling_usher_desent_palmer_franzon_grant_kingon_2000, title={High displacement piezoelectric actuators: characterization at high load with controlled end conditions}, ISBN={0-7803-5940-2}, ISSN={1099-4734}, DOI={10.1109/ISAF.2000.942427}, abstractNote={Piezoelectric ceramic transducers are characterized by relatively small strains on the order of 0.1%. Methods of achieving larger displacements include mechanical amplifiers and flexural mode actuators, such as unimorphs or bimorphs. A particular type of stressed unimorph flexural actuator, the "THUNDER" actuator, provides enhanced flexural strain. (THUNDER/sup TM/ is a trademark of FACE International Corporation). However, displacement has generally not been characterized as a function of load, which was needed for our application. We found that load and displacement were very sensitive to end conditions, which has also not been reported in the literature. The commercially available THUNDER/sup TM/ model 8-R rectangular actuators were chosen for the research presented here. They were operated in a flexural mode, and used to characterize displacement as a function of load under well-controlled end conditions. Our experimental results show that progressively restrictive end conditions increased the stiffness, ranging from 2.5N/m to 23N/m, which increased the load capabilities of the actuator. In some cases, displacement actually increased as a function of load as well. This enhanced stiffness was obtained at a cost of reduced no-load flexural strain (defined as the ratio of flexural displacement and ceramic length), ranging from 1.08% for free end conditions to 0.2% for highly restricted end conditions. The load bearing capabilities were tested out to 10N for most end conditions.}, booktitle={Proceedings of the 12th IEEE International Symposium on Applications of Ferroelectrics}, publisher={IEEE}, author={Mulling, J. and Usher, T. and Desent, B. and Palmer, J. and Franzon, P. and Grant, E. and Kingon, A.}, year={2000}, pages={745–748} }
 @inproceedings{mehrotra_rao_conte_franzon_2000, title={Leveraging high density packaging for high performance DSP systems}, ISBN={0-7803-6450-3}, DOI={10.1109/EPEP.2000.895485}, abstractNote={The high connectivity of SHOCC (seamless high off-chip connectivity) technology can be exploited to increase the number of memory channels in a DSP system. This paper describes the physical and logical architecture of a high performance FFT system enabled by a combination of high density packaging and good memory management schemes, with an emphasis on signal integrity issues.}, booktitle={Proceedings of the IEEE Electrical Performance on Electronic Packaging}, publisher={IEEE}, author={Mehrotra, P. and Rao, V. and Conte, T. and Franzon, P.}, year={2000}, pages={25–28} }
 @inproceedings{gahide_hodge_oxenham_seyam_franzon_2000, title={Micromachines and textiles: Matching two industries}, ISBN={187037245X}, number={2000}, booktitle={Manchester 2000 CD-ROM: Papers from the 2000 Annual (80th) World Conference of The Textile Institute. April 16-19, 2000}, author={Gahide, S. and Hodge, G. and Oxenham, W. and Seyam, A. M. and Franzon, P. D.}, year={2000} }
 @article{gahide_seyam_hodge_oxenham_franzon_2000, title={Micromachines and textiles: Matching two industries}, volume={31}, journal={Textile Asia}, author={Gahide, S. and Seyam, A. and Hodge, G. and Oxenham, W. and Franzon, P.}, year={2000}, pages={58–66} }
 @inproceedings{nackashi_franzon_2000, title={Moletronics: A circuit design perspective}, volume={4236}, DOI={10.1117/12.418782}, abstractNote={Recently, several mechanisms have been proposed as a basis for designing molecular electronic logic switching elements. Many two terminal molecular devices functioning as diodes have been synthesized with responses similar to silicon devices such as rectifying and resonant tunneling diodes. In this paper, the feasibility of integrating these molecular diodes into current circuit architectures is explored. A series of logic gates and a memory element are simulated based on the voltage-controlled current flow method using the Tour-Reed molecular diode exhibiting negative differential resistance (NDR). HSPICE simulation results are used to illustrate the performance of these devices and to quantify additional component and interconnect requirements. Finally, future system design approaches using molecular components are discussed.}, booktitle={Proceedings of the SPIE 4236, Smart Electronics and MEMS II}, author={Nackashi, D. and Franzon, P.}, year={2000}, pages={80–88} }
 @inproceedings{franzon_1999, title={Accuracy Issues in Full-Chip Extraction}, booktitle={DAC 1999}, author={Franzon, P.}, year={1999} }
 @inproceedings{franzon_1999, title={Design Automation and Design Challenges for Package/Systems}, booktitle={Proceedings of the IEEE Asia Design Automation Conference}, author={Franzon, Paul}, year={1999}, month={Jan}, pages={372} }
 @inproceedings{nakkar_franzon_harding_schwartz_1999, place={New York, NY, USA}, title={Dynamically Programmable Cache, Evaluation and Virtualization}, ISBN={1-58113-088-0}, DOI={10.1145/296399.296506}, abstractNote={No abstract available.}, booktitle={Proceedings ACM/SIGDA FPGA 99}, publisher={ACM}, author={Nakkar, Mouna and Franzon, Paul and Harding, John and Schwartz, David}, year={1999}, pages={246} }
 @article{lo_kauffman_franzon_1999, title={High frequency loss and electromagnetic field distribution for striplines and microstrips}, volume={22}, ISSN={["1521-3323"]}, DOI={10.1109/6040.746538}, abstractNote={A new three-component measured equation of invariance (MEI) boundary condition is developed and applied to the hybrid edge/nodal vector finite element method. The electric field distribution on the cross section of various lossy transmission lines is calculated. The propagation constant of a lossy transmission line with coated conductor strip is also calculated. The three-component MEI boundary condition simulates the field distribution on the artificial boundary for electromagnetic field excited by the surface charge density and the three vector components of the electric current density. Numerical experiments are performed to test the method by comparing calculated transmission loss with the measured data.}, number={1}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Lo, HL and Kauffman, JF and Franzon, PD}, year={1999}, month={Feb}, pages={16–25} }
 @article{pomerleau_bilbro_franzon_1999, place={Piscataway, NJ, USA}, title={Improved delay prediction for on-chip buses}, ISBN={1-58113-092-9}, DOI={10.1109/DAC.1999.781366}, abstractNote={In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its ports. In addition, we propose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation in floorplanners during behavioral synthesis.}, journal={Proceedings of the 1999 Design Automation Conference}, publisher={IEEE}, author={Pomerleau, R. and Bilbro, G. and Franzon, P.}, year={1999}, pages={497–501} }
 @inproceedings{franzon_lui_gloster_schaffer_glaser_stanaski_1999, place={Los Alamitos, CA, USA}, title={Infrastructure and course progression for complex IC design education}, ISBN={0-7695-0312-8}, DOI={10.1109/MSE.1999.787052}, abstractNote={The ability to cope with design complexity is an important skill for computer engineers, especially potential system on a chip design engineers. Complexity has many facets, including gate count, the ability to handle multiple disciplines simultaneously, and the ability to cope with complex CAD tools. Teaching complexity also requires considerable investment in tool flows, design examples and tutorials. Here, the approach used at North Carolina State University, USA, is described and illustrated.}, booktitle={Proceedings of the 1999 IEEE International Conference on Microelectronic Systems Education (MSE'99) `Systems Education in the 21st Century' (Cat.No.99-63794)}, publisher={IEEE Computer Society}, author={Franzon, P.D. and Lui, W. and Gloster, C. and Schaffer, T. and Glaser, A. and Stanaski, A.}, year={1999}, pages={88–89} }
 @inproceedings{duewer_wilson_winick_franzon_1999, title={MEMS-based switches for Digital and RF Switching}, booktitle={Proceedings Advanced Research in VLSI}, author={Duewer, B.E. and Wilson, J.M. and Winick, D.A. and Franzon, P.}, year={1999}, month={Apr}, pages={369–377} }
 @inproceedings{duewer_winick_wilson_palmer_franzon_1999, title={Methodology for Design of Electrostatic MEMS Devices Using the SUMMiT Process}, booktitle={Proceedings of the 45th International Instrumentation Symposium}, author={Duewer, Bruce and Winick, David and Wilson, John and Palmer, Jeremy and Franzon, Paul}, year={1999}, month={May}, pages={511–520} }
 @inproceedings{franzon_duewer_wilson_winick_1999, title={Programmable MEMS Capacitor Arrays}, booktitle={Proceedings SPIE International Symposium on Microelectronics and Micromechanical Systems}, author={Franzon, P.D. and Duewer, B. and Wilson, J. and Winick, D.A.}, year={1999}, month={Nov} }
 @inproceedings{nakkar_glaser_franzon_williams_roberson_rinne_1999, title={Three Dimensional MCM Package Assembly and Analysis}, booktitle={Proceedings of the IEEE/IMAPS Conference on High Density Packaging and MCMS}, author={Nakkar, M. and Glaser, A.W. and Franzon, P. and Williams, K. and Roberson, M. and Rinne, G.}, year={1999}, month={May}, pages={188–192} }
 @misc{al-sarawi_abbott_franzon_1998, title={A review of 3-D packaging technology}, volume={21}, ISSN={["1070-9894"]}, DOI={10.1109/96.659500}, abstractNote={This paper reviews the state-of-the-art in three-dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in detail. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, and are briefly discussed.}, number={1}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING}, author={Al-Sarawi, SF and Abbott, D and Franzon, PD}, year={1998}, month={Feb}, pages={2–14} }
 @inproceedings{chaudhury_franzon_1998, title={Accurate Lumped-Parameter modeling for dynamic simulation of electrostatic MEMS Actuators}, booktitle={Proceedings International Workshop on Modeling of MEMS Systems}, author={Chaudhury, S.P. and Franzon, P.D.}, year={1998}, month={Apr} }
 @inproceedings{nakkar_bentlage_harding_schwartz_franzon_conte_1998, title={Dynamically Programmable Cache}, booktitle={Proceedings of the SPIE Conference on Reconfigurable Computing}, author={Nakkar, Mouna and Bentlage, David G. and Harding, John and Schwartz, David and Franzon, Paul and Conte, Thomas}, year={1998}, month={Oct}, pages={218–226} }
 @inproceedings{lipa_glaser_franzon_1998, title={Flip-chip Power Distribution}, ISBN={0-7803-4965-2}, DOI={10.1109/EPEP.1998.733745}, abstractNote={By using thin-film (MCM-D) and flip-chip solder bump technologies to distribute power and ground to an IC, the percentage of metal fill required on the power and ground layers can be reduced. However, significant reductions require a very dense solder bump technology.}, booktitle={Proceedings of the IEEE 7th Topical Meeting on the Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Lipa, S. and Glaser, A.W. and Franzon, P.D.}, year={1998}, pages={39–41} }
 @inproceedings{schaffer_lipa_glaser_franzon_1998, title={Issues in Chip-Package Codesign with MCM-D/Flip-Chip Technology}, ISBN={0-8186-8433-X}, DOI={10.1109/IPDI.1998.663634}, abstractNote={By distributing on-chip global power, ground, and clock planes on a thin film MCM, the IC can be made smaller, faster, and less noisy while consuming less power. These advantages are demonstrated by a number of case studies: two demonstrator ICs and an analysis of the DEC Alpha 21264 clock distribution scheme. However, there are a number of practical issues that need to be addressed, including process variations and test. In this paper, we present the case studies and a treatment of these practical issues.}, booktitle={Proceedings of the IEEE International Symposium on Chip-Package Codesign}, publisher={IEEE}, author={Schaffer, J.T. and Lipa, S. and Glaser, A. and Franzon, P.}, year={1998}, month={Feb}, pages={88–92} }
 @inproceedings{winick_duewer_chaudry_wilson_ticker_eksi_franzon_1998, title={MEMS-based diffractive optical beam steering system}, volume={3276}, DOI={10.1117/12.302411}, abstractNote={This paper presents some results from phase-1 research into developing a beam steerer based on micro-mechanical diffractive elements. The position of these elements is electrostatically controlled, to allow dynamic programming of a 2D phase function. Feasibility prototypes were constructed in the MUMPs polysilicon surface micromachine process.}, booktitle={Proceedings SPIE 3276, Miniaturized Systems with Micro-Optics and Micromechanics III}, publisher={SPIE}, author={Winick, David A. and Duewer, Bruce E. and Chaudry, Som and Wilson, John M. and Ticker, John and Eksi, Umut and Franzon, Paul D.}, year={1998}, month={Mar}, pages={81–87} }
 @inproceedings{azam_evans_franzon_1998, title={Power Reduction by low activity datapath design and SRAM energy models}, booktitle={Proceedings  Workshop on Low Power Techniques, ISCA98}, author={Azam, M. and Evans, R. and Franzon, P.D.}, year={1998}, month={Jul} }
 @inproceedings{schaffer_stanaski_glaser_franzon_1998, title={The NCSU Design Kit for IC Fabrication Through MOSIS}, booktitle={Proceedings 1998 International Cadence User Group Conference}, author={Schaffer, T. and Stanaski, A. and Glaser, A. and Franzon, P.}, year={1998}, pages={71–80} }
 @inproceedings{glaser_nakkar_franzon_conte_rinne_roberson_rogers_williams_1997, title={A Low-cost, High Performance Three-Dimensional Memory Module}, ISBN={0-8186-8099-7}, ISSN={1087-4852}, DOI={10.1109/MTDT.1997.619387}, abstractNote={We present a new interconnect/chip-attach technology that provides high volumetric efficiency for systems that are not I/O bound, while also providing low weight, good thermal management and low cost. This attach technology, perpendicular chip attach, is well-suited for applications such as memory modules, mixed-signal systems integration, and high-density microelectromechanical systems (MEMS).}, booktitle={Proceedings of the IEEE Memory Technology, Design and Testing Workshop}, publisher={IEEE}, author={Glaser, A.W. and Nakkar, M. and Franzon, P.D. and Conte, T.M. and Rinne, G. and Roberson, M. and Rogers, V. and Williams, C.K.}, year={1997}, month={Aug}, pages={2–7} }
 @inproceedings{mcclellan_wailes_franzon_1997, title={An accurate, computationally efficient crosstalk model for routing high-speed MCMs}, booktitle={Proceedings ASIC Conference and Exhibit}, author={McClellan, K.J. and Wailes, T.S. and Franzon, P.D.}, year={1997}, pages={110–114} }
 @article{hseih_liu_franzon_cavin_1997, title={Clocking Optimization and Distribution of Digital Systems with Scheduled Skews}, volume={16}, journal={International Journal of VLSI Signal Processing}, author={Hseih, H.Y. and Liu, W. and Franzon, P. and Cavin, R.}, year={1997}, month={Apr}, pages={19–36} }
 @article{hsieh_liu_franzon_cavin_1997, title={Clocking optimization and distribution in digital systems with scheduled skews}, volume={16}, ISSN={["0922-5773"]}, DOI={10.1023/A:1007934922990}, number={2-3}, journal={JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY}, author={Hsieh, HY and Liu, WT and Franzon, P and Cavin, R}, year={1997}, pages={131–147} }
 @inproceedings{biswas_glasser_lipa_steer_franzon_griffis_russell_1997, title={Experimental Electrical Characterization of On-Chip Interconnects}, DOI={10.1109/EPEP.1997.634038}, abstractNote={This paper describes the transmission line and capacitance measurements made on a 0.25 micron test chip. Transmission lines were characterized to frequencies up to 20 GHz using a Hewlett Packard network analyzer and capacitances were determined using conventional capacitance meter. These measurements will help to develop benchmark capacitance and resistance values of on-chip interconnect structures. Measurements of the physical dimension of the interconnect structures will facilitate the determination of the effects of geometric assumptions made by capacitance extraction tools.}, booktitle={Proceedings of the IEEE Topical Meeting on Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Biswas, Baribrata and Glasser, Allen and Lipa, Steven and Steer, Michael and Franzon, Paul and Griffis, Dieter and Russell, Phillip}, year={1997}, month={Oct}, pages={57–59} }
 @inproceedings{azam_franzon_conte_1997, title={Low Power Data Processing by Elimination of Redundant Computations}, booktitle={Proceedings 1997 International Symposium on Low Power Electronics and Design}, author={Azam, M. and Franzon, P. and Conte, T.}, year={1997}, pages={259–264} }
 @inproceedings{schaeffer_glaser_lipa_franzon_1997, title={MCM Implementation of a Data Encryption Standard (DES) Processor}, booktitle={Proceedings of the 1997 IEEE MCM Conference}, author={Schaeffer, Toby and Glaser, Alan and Lipa, Steve and Franzon, Paul}, year={1997}, pages={13–17} }
 @inproceedings{hansford_peltier_franzon_lipa_schaeffer_1997, title={MIDAS Flip-Chip Service}, booktitle={Proceedings of the 1997 IEEE MCM Conference}, author={Hansford, Wes and Peltier, Jennifer and Franzon, Paul and Lipa, Steve and Schaeffer, Jonathan}, year={1997}, pages={133–135} }
 @inproceedings{winick_duewer_palchaudhury_franzon_1997, title={Performance Evaluation of Micromechanical Binary Phase-Only Holographic Optical Elements}, ISBN={0-7803-3857-X}, ISSN={0569-5503}, DOI={10.1109/ECTC.1997.606204}, abstractNote={This paper presents some results of our development and test efforts in micromachined design for optical modulation. In this work, we have developed, using a readily available surface micromachining fabrication process (MUMPs), a series of arrayed micromirror elements. These element arrays form phase-mostly spatial light modulators (SLMs), similar to Texas Instruments' flexure beam micromirror device (FBMD). Characteristics that distinguish our elements from those of TI include: integrated support posts to stabilize the elements at points beyond pull-in potential, non-metallic supporting structures to reduce diffractive noise, bistable drive capabilities without the need for transistor arrays, and greater mirror surface stability. Firstly, our elements electromechanically bistable MEMS pistons (EmBMPs), are described and their arrayed operation is discussed. Optical evaluations measure the feasibility of these devices in the application of optical interconnections.}, booktitle={Proceedings of the IEEE Electronic Technology and Components Conference}, publisher={IEEE}, author={Winick, D.A. and Duewer, B.E. and Palchaudhury, S. and Franzon, P.D.}, year={1997}, month={May}, pages={419–424} }
 @inproceedings{mcclellan_wailes_franzon_1997, title={Simulation vs. Calculation of Crosstalk}, DOI={10.1109/EPEP.1997.634055}, abstractNote={A crosstalk model for high speed MCMs that is shown to be accurate is compared to simulating a design. Results are presented that show that even though the model is accurate, accurate results cannot be obtained without accounting for timing.}, booktitle={Proceedings of the IEEE Topical Meeting on Electrical Performance of Electronic Packaging}, author={McClellan, K.J. and Wailes, T.S. and Franzon, P.D.}, year={1997}, month={Oct}, pages={131–134} }
 @inproceedings{nakkar_franzon_glaser_rogers_willimas_rinne_1997, title={Thermal/mechanical analysis and design of three dimensional high density MCM package}, booktitle={Proceedings of the Next Generation Package Design Workshop}, author={Nakkar, Mouna and Franzon, Paul and Glaser, A.W. and Rogers, V. and Willimas, K.C. and Rinne, Glenn}, year={1997}, month={Jun} }
 @inproceedings{franzon_conte_banerjia_glaser_lipa_schaffer_stanaski_tekmen_1996, title={Computer Design Strategy for MCM-D/Flip-Chip Technology}, booktitle={Proceedings of the 1996 Topical Meeting on Electrical Performance of Electronic Packaging}, author={Franzon, Paul D. and Conte, Tom and Banerjia, Sanjeev and Glaser, Alan and Lipa, Steve and Schaffer, Toby and Stanaski, Andrew and Tekmen, Yusuf}, year={1996}, month={Oct}, pages={6–8} }
 @inproceedings{franzon_1996, title={Computer Design Strategy for MCM-D/Flip-Chip Technology}, booktitle={Proceedings of the 1996 ASIC Conference}, author={Franzon, P.}, year={1996}, month={Oct}, pages={35–39} }
 @article{lipa_steer_cangellaris_franzon_1996, title={Experimental Characterization of Transmission Lines in Thin-Film Multichip Modules}, volume={19}, number={1}, journal={IEEE Trans. on Components Hybrids and Manufacturing Technology Part A}, author={Lipa, S. and Steer, M.B. and Cangellaris, A.C. and Franzon, P.D.}, year={1996}, month={Feb}, pages={74–82} }
 @book{cho_franzon_1996, title={High Performance Design Automation for Multi-Chip Modules and Packages}, publisher={World Scientific}, author={Cho, J.-D. and Franzon, P.D.}, year={1996} }
 @inproceedings{lakhani_deutschle_franzon_1996, title={High Speed Bus Design Using HSPICE Optimization Techniques Based on Worst Case Design Approach}, booktitle={Proceedings of the 1996 Topical Meeting on Electrical Performance of Electronic Packaging}, author={Lakhani, Raj and Deutschle, Craig and Franzon, Paul}, year={1996}, month={Oct}, pages={93–96} }
 @inproceedings{banerjia_glaser_harvatis_lipa_pomerleau_schaffer_stanaski_tekmen_bilbro_franzon_et al._1996, title={Issues in Partitioning Integrated Circuits for MCM-D/Flip-Chip Technology}, ISBN={0-8186-7286-2}, DOI={10.1109/MCMC.1996.510787}, abstractNote={In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.}, booktitle={Proceedings of the 1996 IEEE MultiChip Module Conference}, publisher={IEEE}, author={Banerjia, Sanjeev and Glaser, Alan and Harvatis, Christoforos and Lipa, Steve and Pomerleau, Real and Schaffer, Toby and Stanaski, Andrew and Tekmen, Yusuf and Bilbro, Grif and Franzon, Paul and et al.}, year={1996} }
 @inbook{franzon_1996, title={Multichip Module Technology}, booktitle={The Electronic Handbook}, publisher={CRC Press}, author={Franzon, P.}, editor={Whitaker, J.Editor}, year={1996} }
 @inproceedings{harvatis_tekmen_bilbro_franzon_1996, title={Pin Assignment for High-Performance MCM Systems}, ISBN={0-7803-3073-0}, DOI={10.1109/ISCAS.1996.542138}, abstractNote={A very fast and efficient pin assignment strategy and algorithm for the early design phase of high-performance Multi-Chip-Modules (MCM) is proposed, which minimizes total wire length, white satisfying the timing constraints. Different delay models are used for on- and off-chip nets for an accurate delay estimation. The proposed pin assignment methodology is applied to a Superscalar Microprocessor design partitioned on an MCM to show that the final design most likely converges to a good result with only a few iterations.}, booktitle={Proceedings of the 1996 IEEE ISCAS Conference}, publisher={IEEE}, author={Harvatis, Christoforos and Tekmen, Yusuf C. and Bilbro, Grif L. and Franzon, Paul D.}, year={1996}, pages={771–774} }
 @inproceedings{franzon_1996, title={System Design Optimization With Multichip Module Technology}, booktitle={Proceedings 1996 Conference of the Brazilian Microelectronics Society}, author={Franzon, P.}, year={1996} }
 @inproceedings{winick_teague_franzon_1995, title={A Micro-machined Approach to Optical Interconnect}, booktitle={Proceedings 1995 Electronic Components and Technology Conference}, author={Winick and Teague, M. and Franzon, P.}, year={1995}, pages={620–627} }
 @article{evans_franzon_1995, title={Energy consumption modeling and optimization for SRAM's}, volume={30}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/4.384170}, DOI={10.1109/4.384170}, abstractNote={The recent trends in portable computing technologies have established the need for energy efficient design strategies. To achieve minimum energy design goals, system designers need a technique to accurately model the energy consumption of their design alternatives without performing a full physical design and full-circuit simulation. This paper presents and compares five approaches for modeling the energy consumption of CMOS circuits. These five modeling approaches have been chosen to represent the various levels of model complexity and accuracy found in the current literature. These modeling approaches are applied to the energy consumption of SRAM's to provide examples of their use and to allow for the comparison of their modeling qualities. It was found that a mixed characterization model-using a CV/sup 2/ prediction for digital subsections and fitted simulation results for the analog subsections-is satisfactory (within /spl plusmn/1 process variation) for predicting the absolute energy consumed per cycle. This same model is also very good (within 2%) for predicting an optimum organization for the internal structures of the SRAM. Several common architectures and circuit designs for SRAM's are analyzed with these models. This analysis shows that global, rather than local improvements, produce the largest energy savings. >}, number={5}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Evans, R.J. and Franzon, P.D.}, year={1995}, month={May}, pages={571–579} }
 @inproceedings{glaser_steer_franzon_1995, title={Measurement of on-IC Capacitance Structures}, booktitle={Proceedings of the 1995 IEEE Topical Meeting on Electrical Performance of Electronic Packaging}, author={Glaser, A.W. and Steer, M.B. and Franzon, P.D.}, year={1995} }
 @inproceedings{franzon_1995, title={Optimal System Design with MultiChip Module Technology}, booktitle={Proceedings of Microeletronics'95}, author={Franzon, P.}, year={1995} }
 @inproceedings{mehrotra_franzon_steer_1995, title={Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs}, booktitle={Proceedings 1995 Design Automation Conference}, author={Mehrotra, Sharad and Franzon, Paul and Steer, Michael}, year={1995}, pages={36–40} }
 @inbook{mehrotra_franzon_1995, title={Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs}, booktitle={Advanced Routing of Electronic Modules}, publisher={Kluwer}, author={Mehrotra, S. and Franzon, P.}, editor={Pecht, M.Editor}, year={1995} }
 @article{basel_steer_franzon_1995, title={Simulation of high speed interconnects using a convolution-based hierarchical packaging simulator}, volume={18}, ISSN={1070-9894}, DOI={10.1109/96.365492}, abstractNote={A specialized packaging simulator is presented which uses an impulse response model of the interconnect network to model high speed digital systems. Behavioral models of drivers and receivers are used. A hierarchical strategy is developed which uses point modeling of discontinuities and the concept of coupling groups to facilitate tradeoffs between accuracy and run time. A new impulse response/convolution technique is developed to efficiently handle large distributed interconnect networks. With this technique, impulse response thresholding provides a smooth transition from delay modeling of interconnects to full distributed circuit simulation. >}, number={1}, journal={IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B}, author={Basel, M. S. and Steer, M. B. and Franzon, P. D.}, year={1995}, month={Feb}, pages={74–82} }
 @inproceedings{franzon_stanaski_tekmen_banerjia_1995, title={System Design Optimization for MCM}, ISBN={0-8186-6970-5}, DOI={10.1109/MCMC.1995.512017}, abstractNote={Many performance/cost advantages can be gained if a chip-set is optimally redesigned to take advantage of the high wire density, fast interconnect delays, and high pin-counts available in MCM-D/flip-chip technology. Examples are given showing for what conditions the cost of the system can be reduced through chip partitioning and how the performance/cost of a computer core can be increased by 81%.}, booktitle={Proceedings of the 1995 IEEE MultiChip Module Conference}, publisher={IEEE}, author={Franzon, Paul and Stanaski, Andrew and Tekmen, Yusuf and Banerjia, Sanjeev}, year={1995} }
 @article{franzon_stanaski_tekmen_banerjia_1995, title={System design optimization for MCM-D/flip-chip}, volume={18}, ISSN={1070-9894}, url={http://dx.doi.org/10.1109/96.475267}, DOI={10.1109/96.475267}, abstractNote={Many performance/cost advantages can be gained if a chip-set is optimally redesigned to take advantage of the high wire density, fast interconnect delays, and high pin-counts available in MCM-D/flip-chip technology. Examples are given showing for what conditions the cost of the system can be reduced through chip partitioning and how the performance/cost of a computer core can be increased. >}, number={4}, journal={IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Franzon, P.D. and Stanaski, A. and Tekmen, Y. and Banerjia, S.}, year={1995}, pages={620–627} }
 @inproceedings{winick_teague_franzon_1994, title={Applications of MEMS to Reconfigurable Free Space Optical Interconnect}, booktitle={Proceedings NSF Optical Packaging Workshop}, author={Winick, D. and Teague, M. and Franzon, P.}, year={1994} }
 @inproceedings{sengupta_lipa_franzon_steer_1994, title={Control of Crosstalk Noise}, booktitle={Proceedings of the 1994 ECTC Conference}, author={Sengupta, M. and Lipa, S. and Franzon, P. and Steer, M.}, year={1994} }
 @article{simovich_mehrotra_franzon_steer_1994, title={Delay and reflection noise macromodeling for signal integrity management of PCBs and MCMs}, volume={17}, ISSN={1070-9894}, url={http://dx.doi.org/10.1109/96.296426}, DOI={10.1109/96.296426}, abstractNote={The current approaches to generating wiring rules for high speed PCBs and MCMs are unsatisfactory because they require intensive manual efforts or use over-simplifications In this paper, an automated approach based on a-priori simulation-based characterization of the interconnect circuit configurations is presented. The improved flexibility and accuracy provided by this approach, when compared with traditional approaches, are demonstrated via an MCM interconnect example. >}, number={1}, journal={IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Simovich, S. and Mehrotra, S. and Franzon, P. and Steer, M.}, year={1994}, pages={15–21} }
 @article{ma_franzon_1994, title={Energy control and accurate delay estimation in the design of CMOS buffers}, volume={29}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/4.309914}, DOI={10.1109/4.309914}, abstractNote={The purpose of this paper is to present a computer aided method to design CMOS multistage variable-taper buffers with optimum energy efficiencies while satisfying speed requirements. The resulting designs typically save at least 20-30% energy per computation over conventionally designed circuits with the same speed. We also present a technique for obtaining accurate empirical delay equations for buffers. >}, number={9}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Ma, Sha and Franzon, P.}, year={1994}, pages={1150–1153} }
 @article{washabaugh_franzon_nagle_1994, title={SABSA: Switching-Activity Based State Assignment}, volume={5}, number={2}, journal={International Journal of High Speed Electronics and Systems}, author={Washabaugh, S. and Franzon, P.D. and Nagle, H.T.}, year={1994}, pages={203–212} }
 @inproceedings{mehrotra_franzon_liu_1994, title={Skew and Delay Minimization of High Speed CMOS Circuits using Stochastic Optimization}, booktitle={Proceedings of the 1994 Custom Integrated Circuits Conference}, author={Mehrotra, S. and Franzon, P. and Liu, W.}, year={1994}, pages={45–48} }
 @inproceedings{mehrotra_franzon_liu_1994, place={New York, NY, USA}, title={Stochastic OptimizationApproach to Transistor Sizing for CMOS Circuits}, ISBN={0-89791-653-0}, DOI={10.1145/196244.196265}, abstractNote={A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with the designer determining when the search is stopped. Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems.}, booktitle={Proceedings of the 1994 IEEE Design Automation Conference}, publisher={ACM}, author={Mehrotra, S. and Franzon, P. and Liu, W.}, year={1994}, pages={36–40} }
 @article{doane_franzon_1994, title={The Case for MCMs}, journal={Semiconductor International}, author={Doane, D. and Franzon, P.}, year={1994}, month={Apr}, pages={85–86} }
 @inproceedings{simovich_mehrotra_franzon_steer_rakib_simpson_1993, title={A Signal Integrity Advisor for Automated Packaging Design}, ISBN={0-7803-1427-1}, DOI={10.1109/EPEP.1993.394591}, abstractNote={A new methodology is presented in which the signal integrity engineer and the design engineer interact with automation tools to produce a printed circuit board (PCB) or multi-chip module (MCM) layout. The focus is on how the signal integrity engineer uses these tools for greatest success.<<ETX>>}, booktitle={Proceedings of the 1993 IEEE Topical Meeting on Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Simovich, Slobodan and Mehrotra, Sharad and Franzon, Paul and Steer, Michael and Rakib, Zaki and Simpson, Garrett}, year={1993} }
 @article{dalal_franzon_lorenzetti_1993, title={A layout-driven yield predictor and fault generator for VLSI}, volume={6}, ISSN={0894-6507}, url={http://dx.doi.org/10.1109/66.210661}, DOI={10.1109/66.210661}, abstractNote={The authors present an efficient approach to probability-graded fault list generation, and critical area calculation for IC yield production. The approach is also efficient to program because it is built on top of existing design rule checking routines. The accuracy of the tool is enhanced by including in the critical area calculations adjustments for defects occurring at the end of a feature and validating shorts before including the associated critical area in the sum. It would be possible to make the approach more efficient by going to an entirely graph-based approach, thus avoiding the physical tile generation step. >}, number={1}, journal={IEEE Transactions on Semiconductor Manufacturing}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Dalal, A.R. and Franzon, P.D. and Lorenzetti, M.J.}, year={1993}, pages={77–82} }
 @inproceedings{simovich_franzon_1993, title={A simple method for noise tolerance characterization of digital circuits}, booktitle={Proceedings 1993 Great Lakes VLSI Conference}, author={Simovich, Slobodan and Franzon, Paul}, year={1993} }
 @article{franzon_evans_1993, title={An MCM Design Process with Application to a Laptop Computer Design}, volume={26}, number={4}, journal={IEEE Computer Magazine}, author={Franzon, P. and Evans, R.}, year={1993}, month={Apr}, pages={41–49} }
 @inproceedings{franzon_simovich_mehrotra_steer_1993, title={Automatic A-Priori Generation of Delay and Noise Macromodels and Wiring Rules for MCMs}, ISBN={0-8186-3540-1}, DOI={10.1109/MCMC.1993.302129}, abstractNote={The authors point out that the current approaches to generating wiring rules for high speed MCMs are unsatisfactory because they require intensive manual efforts to generate and they present an automated approach based on a-priori simulation-based characterization of the interconnect circuit configurations. The improved flexibility and accuracy provided by this approach, when compared with the rule of thumb approach, are demonstrated via an example.<<ETX>>}, booktitle={Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93}, publisher={IEEE}, author={Franzon, Paul and Simovich, Slobodan and Mehrotra, Sharad and Steer, Michael}, year={1993} }
 @inproceedings{cook_harcourt_miller_franzon_1993, title={Behavioral modeling of processors from instruction set specifications}, booktitle={Open Verilog International 1993 Conference}, year={1993} }
 @article{lipa_steer_morris_franzon_1993, title={Comparison of methods for determining the capacitance of planar transmission lines with application to multichip module characterization}, journal={IEEE Trans. on Components Hybrids and Manufacturing Technology/Advanced Packaging}, author={Lipa, S. and Steer, M.B. and Morris, A.S. and Franzon, P.D.}, year={1993}, month={May} }
 @inproceedings{bowen_bahler_franzon_1993, title={Design advice systems for concurrent engineering: A constraint-based approach}, author={Bowen, J. and Bahler, D. and Franzon, P.}, year={1993}, month={Jan} }
 @inproceedings{steer_lipa_franzon_1993, title={Experimental characterization of interconnects and discontinuities in thin-film multichip module substrates}, ISBN={0-7803-1427-1}, DOI={10.1109/EPEP.1993.394569}, abstractNote={Interconnects and discontinuities in a thin-film multichip module substrate are experimentally characterized, taking into account the effective dielectric loss attributed to dielectric anisotropy of the thin-film.<<ETX>>}, booktitle={Proceedings of the 1993 IEEE Topical Meeting on Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Steer, M. and Lipa, S. and Franzon, P.}, year={1993} }
 @inproceedings{cook_franzon_miller_1993, title={LISAS: A Language for Instruction Set Architecture Specification}, booktitle={Proceedings 1993 ICCD Conference}, author={Cook, Todd A. and Franzon, P.D. and Miller, Thomas K., III}, year={1993}, pages={552–557} }
 @inproceedings{franzon_simovich_mehrotra_steer_1993, title={Macromodels for Generating Signal Integrity and Timing Management Advice for Package Design}, ISBN={0-7803-0794-1}, DOI={10.1109/ECTC.1993.346796}, abstractNote={The electrical design of packaging for high speed digital systems requires intensive efforts on the part of signal integrity engineers. We have produced a set of tools that assist these engineers in efficiently producing PCB and MCM designs that meet timing and other electrical needs. This paper describes the most important aspect of this solution, the internal 'macromodels' that accurately capture the relationships between electrical/timing design and the package physical design (or layout).<<ETX>>}, booktitle={Proceedings of the IEEE 1993 ECTC Conference}, publisher={IEEE}, author={Franzon, Paul and Simovich, Slobodan and Mehrotra, Sharad and Steer, Michael}, year={1993}, pages={523–529} }
 @article{simovich_franzon_steer_1993, title={Method for automated waveform analysis of transient in digital circuits}, volume={29}, number={8}, journal={Electronics Letters}, author={Simovich, S. and Franzon, P.D. and Steer, M.B.}, year={1993}, month={Apr}, pages={681–693} }
 @book{doane_franzon_1993, title={Multichip Modules: Basics and Alternatives}, publisher={Van Nostrand Rheinhold}, author={Doane, D. and Franzon, P.}, year={1993} }
 @inbook{franzon_steer_1993, title={Tools and Techniques for the Design of High Speed Multichip Modules, Chapter 7}, volume={3}, booktitle={Electronics Packaging Forum}, publisher={IEEE Press}, author={Franzon, P. and Steer, Michael}, editor={Morris, J.Editor}, year={1993} }
 @inproceedings{dholakia_lee_bitzer_vouk_wang_franzon_1992, place={New York, NY, USA}, title={An efficient table-driven decoder for one-half rate convolutional codes}, ISBN={0-89791-506-2}, DOI={10.1145/503720.503759}, abstractNote={Error control schemes are becoming increasingly important as the needs increase for very high rates of data transmission over inherently noisy channels (e.g. satellite and spread-spectrum communication). Forward error-correction is one means of improving channel performance, but at high data transmission rates very efficient decoder implementations are required. In this paper, we describe an efficient table-driven decoder for 1/2-rate nonsystematic convolutional codes. Various decoder implementation and performance issues are discussed.}, booktitle={ACM-SE 30 Proceedings of the 30th annual Southeast regional conference}, publisher={ACM}, author={Dholakia, A. and Lee, T.M. and Bitzer, D.L. and Vouk, M.A. and Wang, L. and Franzon, P.D.}, year={1992}, pages={116–123} }
 @inproceedings{franzon_mehrotra_simovich_steer_1992, title={Automating Design for Signal Integrity}, ISBN={0-7803-0683-X}, DOI={10.1109/EPEP.1992.572251}, booktitle={Proceedings 1992 IEEE Topical Meeting on Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Franzon, P.D. and Mehrotra, M. and Simovich, S. and Steer, M.}, year={1992}, pages={10–13} }
 @article{steer_goldberg_franzon_1992, title={Comment on an accurate measurement technique for line properties, junction effects and dielectric and magnetic parameters}, journal={IEEE Transactions on Microwave Theory Tech}, author={Steer, M.B. and Goldberg, S.B. and Franzon, P.D.}, year={1992}, month={Feb} }
 @inproceedings{vardaman_hartnett_ng_franzon_1992, title={Cost/performance issues in multichip module packaging}, booktitle={Proceedings of the Japan International Conference on Microelectronics}, author={Vardaman, E.J. and Hartnett, M.W. and Ng, L.H. and Franzon, P.D.}, year={1992} }
 @inproceedings{steer_goldberg_rinne_franzon_turlik_kasten_1992, title={Introducing the through-line deembedding procedure}, ISBN={0-7803-0611-2}, ISSN={0149-645X}, DOI={10.1109/MWSYM.1992.188284}, abstractNote={The through-line (TL) method is introduced to replace the through-reflect-line (TRL) deembedding procedure. TL utilizes measurements of two lengths of line following approximate open-short-line calibration. TL accounts for the frequency-dependent characteristic impedance of the line and avoids the periodic glitches inherent in the TRL procedure.<<ETX>>}, booktitle={1992 IEEE MTT-S International Microwave Symposium Digest}, publisher={IEEE}, author={Steer, M.B. and Goldberg, S.B. and Rinne, G. and Franzon, P.D. and Turlik, I. and Kasten, J.S.}, year={1992}, month={Jun} }
 @inproceedings{steer_franzon_1992, title={Microwave characterization of thin-film multi-chip module substrates and printed wiring boards accounting for frequency-dependent characteristic impedance}, ISBN={0-7803-0683-X}, DOI={10.1109/EPEP.1992.572285}, booktitle={Proceedings of the IEEE Topical Meeting on Electrical Performance of Electronic Packaging}, publisher={IEEE}, author={Steer, M. and Franzon, P.D.}, year={1992}, pages={125–127} }
 @inproceedings{franzon_simovich_steer_basel_mehrotra_mills_1992, title={Tools to aid in Wiring Rule Generation for High Speed Interconnects}, booktitle={Proceedings 1992 Design Automation Conference}, author={Franzon, P.D. and Simovich, S. and Steer, M. and Basel, M. and Mehrotra, S. and Mills, T.D.}, year={1992}, pages={466–471} }
 @inproceedings{goldberg_steer_franzon_1991, title={Accurate experimental characterization of three-ports}, ISBN={0-87942-591-1}, ISSN={0149-645X}, DOI={10.1109/MWSYM.1991.146972}, abstractNote={An accurate procedure is reported for experimentally characterizing microwave devices using two-port measurements. Only reflection measurements are used to determine three-port reflection parameters, and transmission measurements are primarily used to determine three-port transmission parameters, thus considerably reducing the sensitivity of the procedure. No assumptions about the three-port device are made. A comparison with the renormalization method of D. Woods (1977) was made using a microstrip tee, and an improvement in accuracy was confirmed.<<ETX>>}, booktitle={Proceedings of the 1991 IEEE MTT-S International Microwave Symposium Digest}, publisher={IEEE}, author={Goldberg, S.B. and Steer, M.B. and Franzon, P.D.}, year={1991}, month={Jun} }
 @inproceedings{franzon_mehrotra_simovich_steer_1991, place={Tucson, Arizona}, title={Automating Design for Signal Integrity}, booktitle={Topical Meeting on Electrical Performance of Electronic Packaging}, author={Franzon, Paul and Mehrotra, Sharad and Simovich, Slobodan and Steer, Michael}, year={1991}, month={Apr} }
 @inproceedings{goldberg_steer_franzon_1991, title={Experimental electrical characterization of high speed interconnects}, booktitle={Proceedings of the 41st Electronic Components and Technology Conference}, author={Goldberg, S.B. and Steer, M.B. and Franzon, P.D.}, year={1991}, month={May} }
 @article{goldberg_steer_franzon_kasten_1991, title={Experimental electrical characterization of interconnects and discontinuities in high-speed digital systems}, volume={14}, ISSN={0148-6411}, url={http://dx.doi.org/10.1109/33.105130}, DOI={10.1109/33.105130}, abstractNote={Experimental procedures suited to characterization of microstrip and stripline interconnects and discontinuities on printed circuit boards (PCBs) and multichip modules (MCMs) are discussed. Techniques for calibrated two- and three-port measurements using novel calibration schemes are developed. The first of these utilized symmetry to circumvent the problem of inserting reproducible reflection standards. In the second technique, the complex impedance of a line standard was determined. A closed-form algorithm that accurately characterizes a three-port device is introduced as the third technique. >}, number={4}, journal={IEEE Transactions on Components, Hybrids, and Manufacturing Technology}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Goldberg, S.B. and Steer, M.B. and Franzon, P.D. and Kasten, J.S.}, year={1991}, pages={761–765} }
 @inproceedings{basel_steer_franzon_winkelstein_1991, title={High Speed Digital System Simulation using Frequency Dependent Transmission Line Network Modeling}, ISBN={0-87942-591-1}, ISSN={0149-645X}, DOI={10.1109/MWSYM.1991.147176}, abstractNote={A robust and accurate method for the analysis of high-speed digital circuits with a lossy, frequency-dependent transmission line network is presented. Implementation in an analog circuit simulator, using convolution and time-domain scattering parameters, in combination with a linear microwave circuit simulator is discussed.<<ETX>>}, booktitle={Proceedings of the 1991 IEEE MTT-S International Microwave Symposium Digest}, publisher={IEEE}, author={Basel, M.S. and Steer, M.B. and Franzon, P.D. and Winkelstein, D.}, year={1991}, month={Jun} }
 @inproceedings{franzon_steer_1991, title={Interconnect Modeling and Simulation for High Speed MCM}, booktitle={Proceedings Multichip Module Workshop}, author={Franzon, P.D. and Steer, M.B.}, year={1991}, month={Mar}, pages={122–129} }
 @inproceedings{steer_franzon_1991, place={Tucson, Arizona}, title={Microwave characterization of thin-film multi-chip module substrates and printed wiring boards accounting for frequency-dependent characteristic impedance}, booktitle={Topical Meeting on Electrical Performance of Electronic Packaging}, author={Steer, M.B. and Franzon, P.D.}, year={1991}, month={Apr} }
 @inproceedings{van den bout_nagle_miller_franzon_1991, title={The NCSU Design Center}, booktitle={Proceedings of the 1991 Microsystems Educators Conference}, author={Van den Bout, D. and Nagle, T. and Miller, T. and Franzon, P.}, year={1991}, month={Jul} }
 @inproceedings{franzon_steer_1991, title={Tools and Techniques for the Design of High Speed Multichip Modules}, booktitle={Proceedings of the Third Annual Electronics Packaging Symposium}, author={Franzon, P. and Steer, Michael}, year={1991} }
 @inproceedings{franzon_steer_gyurcsik_1991, title={Tools and techniques for the Design of High Speed Multichip Modules}, booktitle={Proceedings Japan IEMT}, author={Franzon, Paul and Steer, Michael and Gyurcsik, Ronald}, year={1991}, month={Jul} }
 @inproceedings{steer_franzon_1990, title={Circuit Simulation with Distributed Elements}, booktitle={Proceedings of the Workshop on Circuit and Process Simulation}, author={Steer, M.B. and Franzon, P.D.}, year={1990} }
 @inproceedings{franzon_van den bout_paulos_miller_snyder_nagle_liu_1990, title={Defect tolerant implementations for feed-forward and recurrent neural networks}, booktitle={Proceedings of 1990 International Conference on Wafer-Scale Integration}, author={Franzon, P. and Van den Bout, D. and Paulos, J. and Miller, T., III and Snyder, W. and Nagle, T. and Liu, W.}, year={1990}, month={Jan}, pages={160–166} }
 @inproceedings{lorenzetti_dalal_franzon_1990, title={McYield: A CAD Tool for Functional Yield Projections for VLSI}, booktitle={1990 International Workshop on Defect and Fault Tolerance in VLSI Systems}, author={Lorenzetti, M. and Dalal, A. and Franzon, P.}, year={1990} }
 @article{van den bout_franzon_paulos_miller_snyder_nagle_liu_1990, title={Scalable VLSI implementations for neural networks}, volume={1}, ISSN={0922-5773}, url={http://dx.doi.org/10.1007/bf00929928}, DOI={10.1007/bf00929928}, number={4}, journal={Journal of VLSI signal processing systems for signal, image and video technology}, publisher={Springer Nature}, author={van den Bout, D. and Franzon, P. and Paulos, J. and Miller, T. and Snyder, W. and Nagle, T. and Liu, W.}, year={1990}, month={Apr}, pages={367–385} }
 @article{franzon_eshraghian_1989, title={Achieving ULSI through defect tolerance}, volume={1}, number={1}, journal={International Journal of Computer Aided VLSI Design}, author={Franzon, P. and Eshraghian, K.}, year={1989}, pages={73–90} }
 @inproceedings{franzon_1989, title={Comparison of Reconfiguration Schemes for Defect Tolerant Mesh Arrays}, booktitle={Proceedings of the 1989 Workshop on Defect Tolerance}, author={Franzon, P.}, year={1989}, month={Oct} }
 @inbook{franzon_1989, title={Comparison of Reconfiguration Schemes for Defect Tolerant Mesh Arrays}, volume={2}, booktitle={Defect and Fault Tolerance in VLSI Systems}, publisher={Plenum}, author={Franzon, P.}, editor={Jain, V.K.Editor}, year={1989} }
 @inbook{hatamian_hornak_little_tewksbury_franzon_1989, title={Fundamental interconnection issues}, volume={1: Packaging}, booktitle={Electronic Materials Handbook}, publisher={ASM International}, author={Hatamian, M. and Hornak, L.A. and Little, T. and Tewksbury, S.K. and Franzon, P.}, year={1989}, pages={1–11} }
 @article{franzon_1989, title={Modeling interconnect yield in reconfigurable circuits}, volume={25}, number={18}, journal={Electronics Letters}, author={Franzon, P.}, year={1989}, month={Aug}, pages={1225–1226} }
 @inbook{franzon_tewksbury_1988, place={North Holland}, title={'Chip Frame’ scheme for reconfigurable mesh-connected arrays}, booktitle={Water Scale Integration II}, author={Franzon, P. and Tewksbury, S.K.}, editor={Lea, R.M.Editor}, year={1988} }
 @article{tewksbury_hatamian_franzon_hornak_siller_lawrence_1987, title={FIR digital filters for high sample rate applications}, volume={25}, ISSN={0163-6804}, url={http://dx.doi.org/10.1109/mcom.1987.1093656}, DOI={10.1109/mcom.1987.1093656}, number={7}, journal={IEEE Communications Magazine}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Tewksbury, S. and Hatamian, M. and Franzon, P. and Hornak, L. and Siller, C. and Lawrence, V.}, year={1987}, month={Jul}, pages={62–72} }
 @inbook{franzon_1987, title={Franzon: Yield Modeling for Fault Tolerant VLSI}, booktitle={Systolic Arrays}, publisher={Adam Hilger}, author={Franzon, P.D.}, editor={Moore, W. and McCabe, A. and Urquhart, R.Editors}, year={1987} }
 @article{hatamian_hornak_little_tewksbury_franzon_1987, title={Fundamental Interconnection Issues}, volume={66}, ISSN={8756-2324}, url={http://dx.doi.org/10.1002/j.1538-7305.1987.tb00215.x}, DOI={10.1002/j.1538-7305.1987.tb00215.x}, abstractNote={This paper presents several current interconnection issues as well as future technological directions for improved interconnection/communication performance. The physical hierarchy of interconnections and the corresponding communication environment are highlighted. General issues concerning chip-to-chip and on-chip interconnections are reviewed, with particular emphasis on chip or wafer-level clock distribution. Finally, wafer-scale related system modules and optical interconnections are discussed from a “macro-integration” perspective.}, number={4}, journal={AT&T Technical Journal}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hatamian, Mehdi and Hornak, Lawrence A. and Little, Trevor E. and Tewksbury, Stuart K. and Franzon, Paul}, year={1987}, month={Jul}, pages={13–30} }
 @inproceedings{franzon_tewksbury_1987, place={Uxbridge, England}, title={`Chip Frame' scheme for reconfigurable mesh-connected arrays}, booktitle={Proceedings of the 1987 International workshop on Wafer Scale Integration}, author={Franzon, P. and Tewksbury, S.K.}, year={1987}, month={Sep} }
 @inproceedings{franzon_1986, title={Interconnect Strategies for Fault Tolerant 2D VLSI Arrays}, booktitle={Proceedings of the International Conference on Computer Design}, author={Franzon, P.D.}, year={1986}, month={Oct}, pages={230–234} }
 @inproceedings{hornak_tewksbury_hatamian_ligtenberg_sugla_franzon_1986, title={Through-Wafer Optical Interconnects for Multi-Wafer Wafer-Scale Integrated architectures}, booktitle={Proceedings of SPIE 86}, author={Hornak, L.A. and Tewksbury, S.K. and Hatamian, M. and Ligtenberg, A. and Sugla, B. and Franzon, P.}, year={1986} }
 @inproceedings{franzon_1986, place={England}, title={Yield Modeling for Fault Tolerant VLSI}, booktitle={Proceedings of the International Workshop on Systolic Arrays}, publisher={University of Oxford}, author={Franzon, P.D.}, year={1986}, month={Jul} }
 @inproceedings{eshraghian_bryant_dickinson_fensom_franzon_pope_rockliff_zyner_1985, title={The Transform and Filter Brick: A new architecture for signal processing}, booktitle={Proceedings of the VLSI 85}, author={Eshraghian, K. and Bryant, R.C. and Dickinson, A. and Fensom, D.S. and Franzon, P.D. and Pope, M.T. and Rockliff, J.E. and Zyner, G.}, year={1985} }
 @inproceedings{wyers_qi_franzon, title={A Robust calibration and supervised machine learning reliability framework for digitally-assisted self-healing RFICS}, booktitle={2017 ieee 60th international midwest symposium on circuits and systems (mwscas)}, author={Wyers, E. J. and Qi, W. Y. and Franzon, P. D.}, pages={1138–1141} }
 @misc{franzon_mick_wilson, title={Buried solder bumps for AC-coupled microelectronic interconnects}, volume={6,927,490}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Franzon, P. D. and Mick, S. E. and Wilson, J. M.} }
 @inproceedings{franzon, title={CAD Tools for the Automated Design of High Speed Multichip Modules}, booktitle={Proceedings of the 1990 International Packaging Symposium}, author={Franzon, P.} }
 @inproceedings{mehrotra_franzon_bilbro_steer, title={CAD tools for Managing Signal Integrity and Congestion Simultaneously}, booktitle={Proceedings of the 1994 Topical Meeting on Electrical Performance of Electrical Packaging}, author={Mehrotra, S. and Franzon, P. and Bilbro, G. and Steer, M.}, pages={30–32} }
 @inproceedings{thorolfsson_melamed_charles_franzon, title={Comparative analysis of two 3D integration implementations of a SAR processor}, booktitle={2009 IEEE International Conference on 3d Systems Integration}, author={Thorolfsson, T. and Melamed, S. and Charles, G. and Franzon, P. D.}, pages={25–28} }
 @inproceedings{dey_franzon, title={Design and ASIC acceleration of cortical algorithm for text recognition}, booktitle={2016 29th IEEE International System-on-Chip Conference (SOCC)}, author={Dey, S. and Franzon, P. D.}, pages={114–119} }
 @inproceedings{dey_franzon, title={Design and ASIC acceleration of cortical algorithm for text recognition}, booktitle={2016 29th IEEE International System-on-Chip Conference (SOCC)}, author={Dey, S. and Franzon, P. D.}, pages={114–119} }
 @inproceedings{li_franzon, title={Hardware implementation of hierarchical temporal memory algorithm}, booktitle={2016 29th IEEE International System-on-Chip Conference (SOCC)}, author={Li, W. F. and Franzon, P.}, pages={133–138} }
 @inproceedings{li_franzon, title={Hardware implementation of hierarchical temporal memory algorithm}, booktitle={2016 29th IEEE International System-on-Chip Conference (SOCC)}, author={Li, W. F. and Franzon, P.}, pages={133–138} }
 @misc{franzon_mick_wilson, title={Inductively coupled electrical connectors}, volume={6,885,090}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Franzon, P. D. and Mick, S. E. and Wilson, J. M.} }
 @inproceedings{li_franzon, title={Machine learning in physical design}, booktitle={Ieee conference on electrical performance of electronic packaging and}, author={Li, B. W. and Franzon, P. D.}, pages={147–149} }
 @misc{mehrotra_franzon, title={Methods and systems for fast binary network address lookups using parent node information stored in routing table entries}, volume={6,934,252}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Mehrotra, P. and Franzon, P. D.} }
 @misc{mehrotra_franzon, title={Methods and systems for fast packet forwarding}, volume={6,985,483}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Mehrotra, P. and Franzon, P. D.} }
 @inproceedings{schabel_baker_dey_li_franzon, title={Processor-in-memory support for artificial neural networks}, booktitle={2016 IEEE International Conference on Rebooting Computing (icrc)}, author={Schabel, J. and Baker, L. and Dey, S. and Li, W. F. and Franzon, P. D.} }
 @inproceedings{nigussie_franzon, title={RDL and interposer design for DiRAM4 interfaces}, booktitle={Ieee conference on electrical performance of electronic packaging and}, author={Nigussie, T. and Franzon, P. D.}, pages={17–19} }
 @article{zhao_gadfort_bhanushali_franzon, title={RF-only logic: An area efficient logic family for RF-power harvesting applications}, volume={65}, number={1}, journal={IEEE Transactions on Circuits and Systems. I, Regular Papers}, author={Zhao, W. X. and Gadfort, P. and Bhanushali, K. and Franzon, P. D.}, pages={406–418} }
 @inproceedings{hsieh_lui_clements_franzon, title={Self-calibrating clock distribution with scheduled skews}, volume={2 }, booktitle={Proceedings of ISCAS'98}, author={Hsieh, H.-Y. and Lui, W. and Clements, M. and Franzon, P.}, pages={470–473} }
 @article{burr_franzon, title={Storage class memory}, journal={Emerging Nanoelectronic Devices}, author={Burr, G. W. and Franzon, P.}, pages={498–510} }
 @article{yelten_franzon_steer, title={Surrogate-model-based analysis of analog circuits-part I: Variability analysis}, volume={11}, number={3}, journal={IEEE Transactions on Device and Materials Reliability}, author={Yelten, M. B. and Franzon, P. D. and Steer, M. B.}, pages={466–473} }
 @article{yelten_franzon_steer, title={Surrogate-model-based analysis of analog circuits-part II: Reliability analysis}, volume={11}, number={3}, journal={IEEE Transactions on Device and Materials Reliability}, author={Yelten, M. B. and Franzon, P. D. and Steer, M. B.}, pages={458–465} }
 @inproceedings{oh_franzon, title={Technology impact analysis for 3D TCAM}, booktitle={2009 IEEE International Conference on 3d Systems Integration}, author={Oh, E. C. and Franzon, P. D.}, pages={206–210} }
 @inproceedings{tsai_klooz_leonard_appel_franzon, title={Through silicon Via(TSV) defect/pinhole self test circuit for 3D-IC}, booktitle={2009 IEEE International Conference on 3d Systems Integration}, author={Tsai, M. L. and Klooz, A. and Leonard, A. and Appel, J. and Franzon, P.}, pages={170–177} }
 @book{smith_franzon, title={Verilog styles for synthesis of digital systems}, ISBN={0201618605}, publisher={Upper Saddle River, NJ: Prentice Hall}, author={Smith, D. R. and Franzon, P. D.} }