@inproceedings{chandrasekar_wilson_erickson_feng_xu_mick_franzon_2008, title={Inductively coupled connectors and sockets for multi-Gb/s pulse signaling}, volume={31}, DOI={10.1109/tadvp.2008.2005465}, abstractNote={Multi-Gb/s pulse signaling is demonstrated with inductively coupled interconnects across packaging interfaces. This has application in realizing submillimeter pitch, true zero insertion force (ZIF) surface mount connectors, and sockets. The signaling data rate achieved in this system is from 1 to 8.5 Gbps, which depends on the 3-dB coupling frequency of the composite channel consisting of the inductive interconnections and the transmission lines. This paper presents the results of a set of experiments demonstrating this capability and describes the principles behind the design of inductively coupled sockets and connectors.}, number={4}, booktitle={IEEE Transactions on Advanced Packaging}, author={Chandrasekar, K. and Wilson, J. and Erickson, E. and Feng, Z. P. and Xu, J. and Mick, S. and Franzon, Paul}, year={2008}, pages={749–758} }
 @article{wilson_mick_xu_luo_bonafede_huffman_labennett_franzon_2007, title={Fully integrated AC coupled interconnect using buried bumps}, volume={30}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2007.896920}, abstractNote={Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.}, number={2}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Wilson, John and Mick, Stephen and Xu, Jian and Luo, Lei and Bonafede, Salvatore and Huffman, Alan and LaBennett, Richard and Franzon, Paul D.}, year={2007}, month={May}, pages={191–199} }
 @article{davis_wilson_mick_xu_hua_mineo_sule_steer_franzon_2005, title={Demystifying 3D ICs: The procs and cons of going vertical}, volume={22}, ISSN={["1558-1918"]}, DOI={10.1109/MDT.2005.136}, abstractNote={This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.}, number={6}, journal={IEEE DESIGN & TEST OF COMPUTERS}, author={Davis, WR and Wilson, J and Mick, S and Xu, M and Hua, H and Mineo, C and Sule, AM and Steer, M and Franzon, PD}, year={2005}, pages={498–510} }
 @article{xu_mick_wilson_luo_chandrasekar_erickson_franzon_2004, title={AC coupled interconnect for dense 3-D ICs}, volume={51}, ISSN={["1558-1578"]}, DOI={10.1109/TNS.2004.834712}, abstractNote={This paper presents the potential application of AC coupled interconnect (ACCI) for dense three-dimensional (3-D) integrated circuits (ICs). The concept of inductive ACCI for 3-D ICs has been proposed. Combined with the "through vias" technology, inductive ACCI can provide small pitch vertical interconnects, as well as an excellent thermal solution for dense 3-D ICs. Transformer modeling and transceiver circuit design have also been investigated. Simulations predict that, for 20 /spl mu/m thinned die stacks coupled by a 100 /spl mu/m diameter transformer, the transceiver circuit fed with a 5 Gbps data stream consumes 14.5 mW power.}, number={5}, journal={IEEE TRANSACTIONS ON NUCLEAR SCIENCE}, author={Xu, J and Mick, S and Wilson, J and Luo, L and Chandrasekar, K and Erickson, E and Franzon, PD}, year={2004}, month={Oct}, pages={2156–2160} }
 @article{mick_luo_wilson_franzon_2004, title={Buried bump and AC coupled interconnection technology}, volume={27}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2004.825482}, abstractNote={A novel physical structure, buried solder bumps, is introduced that solves the compliance problems that exist in scaling present area array technologies to ever-higher densities. In this technique, buried bumps provide dc connections between integrated circuits and substrates and ac coupled interconnections provide paths for ac signals across the same interface. This approach requires co-design of packaging and circuits and meets the growing demands for both interconnect density and bandwidth. AC coupled interconnection arrays can be built with pitches for ac signals below 100 /spl mu/m and data rates of 6 Gb/s per I/O. This paper presents the physical and circuit aspects of this work as well as measured results from capacitively-coupled circuits fabricated in Taiwan semiconductor manufacturing Company (TSMC) 0.35-/spl mu/m technology. Simulated results from capacitively-coupled circuits in TSMC 0.18 /spl mu/m are also presented.}, number={1}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Mick, S and Luo, L and Wilson, J and Franzon, P}, year={2004}, month={Feb}, pages={121–125} }
 @article{mohan_choi_mick_hart_chandrasekar_cangellaris_franzon_steer_2004, title={Causal reduced-order modeling of distributed structures in a transient circuit simulator}, volume={52}, ISSN={["1557-9670"]}, DOI={10.1109/TMTT.2004.834588}, abstractNote={Fosters' canonical representation of the transfer characteristic of a linear system is the key to causal fully convergent incorporation of distributed structures in transient circuit simulators. The implementation of the Foster's model in the fREEDA circuit simulator is reported and the modeling of a two-port coupled inductor is presented as an example.}, number={9}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Mohan, R and Choi, MJ and Mick, SE and Hart, FP and Chandrasekar, K and Cangellaris, AC and Franzon, PD and Steer, MB}, year={2004}, month={Sep}, pages={2207–2214} }
 @misc{franzon_mick_wilson, title={Buried solder bumps for AC-coupled microelectronic interconnects}, volume={6,927,490}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Franzon, P. D. and Mick, S. E. and Wilson, J. M.} }
 @misc{franzon_mick_wilson, title={Inductively coupled electrical connectors}, volume={6,885,090}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Franzon, P. D. and Mick, S. E. and Wilson, J. M.} }