Works (3)
Updated: July 5th, 2023 15:43
2013 journal article
Automatic Parallelization of Fine-Grained Metafunctions on a Chip Multiprocessor
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(4).
author keywords: Automatic parallelization; helper computing; chip multiprocessor
TL;DR:
This work considers an automatic thread extraction technique for removing metafunctions from a main application and scheduling them on helper threads, which can leverage the resources available on a CMP to reduce the latency and overhead of fine-grained checking codes.
(via Semantic Scholar)
open access via dl.acm.org (publisher PDF)
Source: Web Of Science
Added: August 6, 2018
2011 conference paper
Automatic Parallelization of Fine-grained Meta-functions on a Chip Multiprocessor
International Symposium on Code Generation and Optimization, 130–140.
TL;DR:
This work considers an automatic thread extraction technique for removing meta-functions from a main application and scheduling them on helper threads, which can leverage the resources available on a CMP to reduce the latency and overhead of fine-grained checking codes.
(via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2011 conference paper
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
International symposium on high-performance computer, 99–110.
TL;DR:
A hardware-accelerated queue, or HAQu, is proposed that adds hardware to a CMP that accelerates operations on software queues, and ensures that the full state of the queue is stored in the application's address space, thereby ensuring virtualization.
(via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018
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