Works (2)
Updated: April 11th, 2023 10:13
2017 conference paper
A case for standard-cell based RAMs in highly-ported superscalar processor structures
Proceedings of the eighteenth international symposium on quality electronic design (isqed), 131–137.
TL;DR:
This paper introduces a standard-cell memory compiler with three key features: (i) per-row clock gating, (ii) a new tri-state based mux standard cell, and (iii) a modular layout strategy, which is the centerpiece of the memory compiler.
(via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018
2016 conference paper
AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores
Ieee international symposium on performance analysis of systems and, 214–224.
TL;DR:
A register-transfer-level (RTL) design of a highly adaptive superscalar core, called AnyCore, which can be used to quantify logic overheads of an adaptive core with respect to fixed cores, synthesize and compare different adaptive cores, and fabricate adaptive supersCalar cores.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: NC State University Libraries
Added: August 6, 2018
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