Samira Mirbagher Ajorpaz

Works (8)

Updated: April 4th, 2024 16:47

2023 journal article

An Attack on The Speculative Vectorization: Leakage from Higher Dimensional Speculation

By: S. Karuppanan & S. Mirbagher Ajorpaz* 

Sources: Crossref, NC State University Libraries
Added: March 16, 2023

2022 article proceedings

Composite Instruction Prefetching

By: G. Chacon *, E. Garza*, A. Jimborean *, A. Ros *, P. Gratz *, D. Jimenez *, S. Mirbagher-Ajorpaz  n

Event: 2022 IEEE 40th International Conference on Computer Design (ICCD)

author keywords: instruction prefetching; hardware prefetching; first-level caches; datacenter applications
TL;DR: This work proposes a framework for selecting and combining state-of-the-art complex prefetchers, in a "plug-and-play" fashion, to identify the best performing combinations at various hardware overheads and shows that for every storage capacity constraint analyzed, compositePrefetching outperforms prior prefetching schemes with greater improvements shown at smaller capacity constraints. (via Semantic Scholar)
Sources: Crossref, NC State University Libraries, Web Of Science
Added: March 16, 2023

2022 article

Dynamic Set Stealing to Improve Cache Performance

2022 IEEE 34TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD 2022), pp. 60–70.

By: B. Testa*, S. Mirbagher-Ajorpaz  n & D. Jimenez *

author keywords: microarchitecture; prediction; cache replacement
TL;DR: Set Stealing with Perceptron Tables (SSPT) is introduced, a novel resource management policy that allows combining the strengths of many replacement policies to maximize performance and eliminate wasted processor resources. (via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries
Added: February 20, 2023

2022 article

EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security

EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security. 2022 55TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), pp. 1218–1236.

By: S. Ajorpaz  n, D. Moghimi *, J. Collins, G. Pokam *, N. Abu-Ghazaleh * & D. Tullsen *

author keywords: Hardware Security; Side channel; Generative Adversarial Networks; Automatic Attack Sample Generation; Adversarial Machine Learning Attacks; Automated Hardware Performance Counter Engineering; Microarchitectural Attack Detection; Linearized Neural Network; ML Interpretability; Zero Day Attack Defense
TL;DR: An approach that reduces the overhead of state-of-art defenses by over 95%, by applying defenses only when attacks are detected, and uses a novel Generative framework, Evasion Vaccination (EVAX) for training ML models and engineering new security-centric performance counters. (via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries
Added: December 12, 2022

2020 article proceedings

CHiRP: Control-Flow History Reuse Prediction

Presented at the 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

By: S. Mirbagher-Ajorpaz *, E. Garza*, G. Pokam * & D. Jimenez *

Event: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

TL;DR: It is shown how predictive replacement policies can be tailored toward TLBs to reduce miss rates and improve overall performance, and introduces a novel TLB-focused predictive policy, Control-flow History Reuse Prediction (CHIRP). (via Semantic Scholar)
Sources: Crossref, NC State University Libraries
Added: March 16, 2023

2020 article proceedings

PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron

Presented at the 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

By: S. Mirbagher-Ajorpaz *, G. Pokam *, E. Mohammadian-Koruyeh*, E. Garza*, N. Abu-Ghazaleh * & D. Jimenez *

Event: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

TL;DR: This study systematically investigates the microarchitectural footprints of hardware-based attacks and shows how they can be detected and classified using an efficient hardware predictor, using perceptron learning to identify and classify attacks. (via Semantic Scholar)
Sources: Crossref, NC State University Libraries
Added: March 16, 2023

2019 conference paper

Bit-level perceptron prediction for indirect branches

Proceedings of the 46th International Symposium on Computer Architecture. Presented at the ISCA '19: The 46th Annual International Symposium on Computer Architecture, Phoenix, AZ.

By: E. Garza, S. Mirbagher-Ajorpaz, T. Khan & D. Jiménez

Event: ISCA '19: The 46th Annual International Symposium on Computer Architecture at Phoenix, AZ

TL;DR: This paper proposes a new indirect branch prediction scheme that predicts target addresses at the bit level using a series of perceptron-based predictors, and shows this new branch target predictor is competitive with state-of-the-art branch target predictors at an equivalent hardware budget. (via Semantic Scholar)
Sources: Crossref, NC State University Libraries
Added: March 16, 2023

2018 article proceedings

Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer

Presented at the 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

By: S. Mirbagher Ajorpaz* , E. Garza*, S. Jindal* & D. Jimenez *

Event: 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)

TL;DR: The effectiveness of GHRP as a dead block replacement and bypass optimization for both the I-cache and BTB is described, performing significantly better than Static Re-reference Interval Prediction (SRRIP) and Sampling Dead Block Prediction (SDBP). (via Semantic Scholar)
Sources: Crossref, NC State University Libraries
Added: March 16, 2023

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