2022 article
LITE: A Low-Cost Practical Inter-Operable GPU TEE
PROCEEDINGS OF THE 36TH ACM INTERNATIONAL CONFERENCE ON SUPERCOMPUTING, ICS 2022.
2021 article
Seeds of SEED: New Security Challenges for Persistent Memory
2021 INTERNATIONAL SYMPOSIUM ON SECURE AND PRIVATE EXECUTION ENVIRONMENT DESIGN (SEED 2021), pp. 83–88.
2020 article
Hardware-Based Domain Virtualization for Intra-Process Isolation of Persistent Memory Objects
2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), pp. 680–692.
2019 journal article
Compiler-support for Critical Data Persistence in NVM
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(4).
2019 journal article
Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2).
2019 conference paper
Exploring Memory Persistency Models for GPUs
28th International Conference on Parallel Architectures and Compilation Techniques (PACT), 310–322.
Event: International Conference on Parallel Architectures and Compilation Techniques at Seattle, WA on September 21-25, 2019
2018 article
Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique
2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 439–451.
2018 article
Scheduling Page Table Walks for Irregular GPU Applications
2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 180–192.
2017 conference paper
Clone morphing: Creating new workload behavior from existing applications
Ieee international symposium on performance analysis of systems and, 97–107.
2017 article
Hiding the Long Latency of Persist Barriers Using Speculative Execution
44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 175–186.
2017 article
ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories
44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 107–119.
2016 article
Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache
MEMSYS 2016: PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MEMORY SYSTEMS, pp. 191–203.
2016 journal article
Significant and sustaining elevation of blood oxygen induced by Chinese cupping therapy as assessed by near-infrared spectroscopy
BIOMEDICAL OPTICS EXPRESS, 8(1), 223–229.
2016 article
Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers
Awad, A., Manadhata, P., Haber, S., Solihin, Y., & Horne, W. (2016, April). ACM SIGPLAN NOTICES, Vol. 51, pp. 263–276.
2016 conference paper
Silent shredder: Zero-cost shredding for secure non-volatile main memory controllers
Operating Systems Review, 50(2), 263–276.
2015 conference paper
Emulating cache organizations on real hardware using performance cloning
Ieee international symposium on performance analysis of systems and, 298–307.
2015 article
MeToo: Stochastic Modeling of Memory Traffic Timing Behavior
2015 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION (PACT), pp. 457–467.
2015 conference paper
Non-volatile memory host controller interface performance analysis in high-performance I/O systems
Ieee international symposium on performance analysis of systems and, 145–154.
2014 chapter
Collaborative Memories in Clusters: Opportunities and Challenges
In Transactions on Computational Science XXII (pp. 17–41).
2014 conference paper
STM : Cloning the spatial and temporal memory access behavior
International symposium on high-performance computer, 237–247.
2012 article
Modeling and Analyzing Key Performance Factors of Shared Memory MapReduce
2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS), pp. 1306–1317.
2012 conference paper
WEST: Cloning data cache behavior using stochastic traces
International symposium on high-performance computer, 387–398.
2011 conference paper
Architectural framework for supporting operating system survivability
International symposium on high-performance computer, 456–465.
2011 journal article
Evaluating Placement Policies for Managing Capacity Sharing in CMP Architectures with Private Caches
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(3).
2011 conference paper
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
International symposium on high-performance computer, 99–110.
2010 chapter
An Analysis of Secure Processor Architectures
In Transactions on Computational Science VII (pp. 101–121).
2010 conference paper
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
International symposium on high-performance computer, 233–244.
2010 journal article
CHOP: INTEGRATING DRAM CACHES FOR CMP SERVER PLATFORMS
IEEE MICRO, 31(1), 99–108.
2010 chapter
Green Secure Processors: Towards Power-Efficient Secure Processor Design
In Transactions on Computational Science X (pp. 329–351).
2010 conference paper
MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management
International Parallel and Distributed Processing Symposium.
2010 journal article
Quality of Service Shared Cache Management in Chip Multiprocessor Architecture
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(3).
2010 conference paper
Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance
International symposium on high-performance computer, 57–68.
2010 journal article
Understanding the Behavior and Implications of Context Switch Misses
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(4).
2009 article
Architecture Support for Improving Bulk Memory Copying and Initialization Performance
18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 169-+.
2009 book
Fundamentals of parallel computer architecture multichip and multicore systems
[United States?]: Solihin Pub.
2009 article
Making Secure Processors OS- and Performance-Friendly
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, Vol. 5.
2009 journal article
MemTracker: An Accelerator for Memory Debugging and Monitoring
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 6(2).
2009 conference paper
Memory Management Thread for Heap Allocation Intensive Applications
Workshop on Memory Performance: Dealing with Applications, Systems Architecture.
2008 journal article
Counter-based cache replacement and bypassing algorithms
IEEE TRANSACTIONS ON COMPUTERS, 57(4), 433–447.
2008 book
Fundamentals of parallel computer architecture
[United States?]: Solihin Pub.
2008 journal article
Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 20(9), 1309–1324.
2006 article
HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, Vol. 50, pp. 261–275.
2005 journal article
Eliminating conflict misses using prime number-based cache indexing
IEEE TRANSACTIONS ON COMPUTERS, 54(5), 573–586.
2003 journal article
Correlation prefetching with a user-level memory thread
IEEE Transactions on Parallel and Distributed Systems, 14(6), 563–580.
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