Works (43)

Updated: July 5th, 2023 15:57

2021 article

Seeds of SEED: New Security Challenges for Persistent Memory

2021 INTERNATIONAL SYMPOSIUM ON SECURE AND PRIVATE EXECUTION ENVIRONMENT DESIGN (SEED 2021), pp. 83–88.

By: N. Ul Mustafa*, Y. Xu n, X. Shen n & Y. Solihin*

author keywords: Persistent memory objects; Security attacks; PMO vulnerability
Sources: Web Of Science, ORCID
Added: June 20, 2022

2020 article

Hardware-Based Domain Virtualization for Intra-Process Isolation of Persistent Memory Objects

2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), pp. 680–692.

By: Y. Xu n, C. Ye*, Y. Solihin* & X. Shen n

author keywords: Persistent Memory Objects; Memory Protection Keys; Intra-process Isolation
Sources: Web Of Science, ORCID
Added: March 8, 2021

2019 journal article

Compiler-support for Critical Data Persistence in NVM

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(4).

By: R. Elkhouly*, M. Alshboul n, A. Hayashi*, Y. Solihin* & K. Kimura*

author keywords: Compiler-support; NVM; data persistence; valid recovery
Source: Web Of Science
Added: January 13, 2020

2019 journal article

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2).

By: M. Alshboul n, H. Elnawawy n, R. Elkhouly*, K. Kimura*, J. Tuck n & Y. Solihin*

author keywords: Memory systems; emerging memory technologies; computer architecture
Source: Web Of Science
Added: August 5, 2019

2019 conference paper

Exploring Memory Persistency Models for GPUs

28th International Conference on Parallel Architectures and Compilation Techniques (PACT), 310–322.

By: Z. Lin n, M. Alshboul n, Y. Solihin* & H. Zhou n

Event: International Conference on Parallel Architectures and Compilation Techniques at Seattle, WA on September 21-25, 2019

Sources: Web Of Science, ORCID
Added: August 10, 2020

2018 article

Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique

2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 439–451.

By: M. Alshboul n, J. Tuck n & Y. Solihin n

author keywords: Emerging Memory Technology; Memory Systems; Multi-core and Parallel Architectures
Source: Web Of Science
Added: March 4, 2019

2018 article

Scheduling Page Table Walks for Irregular GPU Applications

2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 180–192.

By: S. Shin n, G. Cox*, M. Oskin*, G. Loh*, Y. Solihin n, A. Bhattacharjee*, A. Basu*

author keywords: Computer architecture; GPU; Virtual address
Source: Web Of Science
Added: March 4, 2019

2017 conference paper

Clone morphing: Creating new workload behavior from existing applications

Ieee international symposium on performance analysis of systems and, 97–107.

By: Y. Wang n, A. Awad n & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2017 article

Hiding the Long Latency of Persist Barriers Using Speculative Execution

44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 175–186.

By: S. Shin n, J. Tuck n & Y. Solihin n

author keywords: Non-Volatile Main Memory; Speculative Persistence; Failure Safety
Source: Web Of Science
Added: August 6, 2018

2017 article

ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories

44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 107–119.

By: A. Awad*, Y. Wang n, D. Shands* & Y. Solihin n

author keywords: Access Pattern Ofuscation; Hardware Security; ORAM; Emerging Memory Technologies
Source: Web Of Science
Added: August 6, 2018

2017 journal article

Significant and sustaining elevation of blood oxygen induced by Chinese cupping therapy as assessed by near-infrared spectroscopy

BIOMEDICAL OPTICS EXPRESS, 8(1), 223–229.

Source: Web Of Science
Added: August 6, 2018

2016 article

Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache

MEMSYS 2016: PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MEMORY SYSTEMS, pp. 191–203.

By: S. Shin n, S. Kim* & Y. Solihin n

author keywords: Die-stacked DRAM; last-level cache; replacement policy
Source: Web Of Science
Added: August 6, 2018

2016 article

Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers

Awad, A., Manadhata, P., Haber, S., Solihin, Y., & Horne, W. (2016, April). ACM SIGPLAN NOTICES, Vol. 51, pp. 263–276.

By: A. Awad n, P. Manadhata*, S. Haber*, Y. Solihin n & W. Horne*

author keywords: Encryption; Hardware Security; Phase-Change Memory; Data Protection
Source: Web Of Science
Added: August 6, 2018

2016 conference paper

Silent shredder: Zero-cost shredding for secure non-volatile main memory controllers

Operating Systems Review, 50(2), 263–276.

By: A. Awad n, P. Manadhata*, S. Haber*, Y. Solihin n & W. Horne*

Source: NC State University Libraries
Added: August 6, 2018

2015 conference paper

Emulating cache organizations on real hardware using performance cloning

Ieee international symposium on performance analysis of systems and, 298–307.

By: Y. Wang n & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2015 article

MeToo: Stochastic Modeling of Memory Traffic Timing Behavior

2015 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION (PACT), pp. 457–467.

By: Y. Wang n, Y. Solihin* & G. Balakrishnan n

author keywords: workload cloning; memory subsystem; memory controller; memory bus; DRAM
Source: Web Of Science
Added: August 6, 2018

2015 conference paper

Non-volatile memory host controller interface performance analysis in high-performance I/O systems

Ieee international symposium on performance analysis of systems and, 145–154.

By: A. Awad n, B. Kettering* & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2014 chapter

Collaborative Memories in Clusters: Opportunities and Challenges

In Transactions on Computational Science XXII (pp. 17–41).

By: A. Samih*, R. Wang*, C. Maciocco*, M. Kharbutli* & Y. Solihin n

Source: Crossref
Added: February 24, 2020

2014 conference paper

STM : Cloning the spatial and temporal memory access behavior

International symposium on high-performance computer, 237–247.

By: A. Awad n & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2012 article

Modeling and Analyzing Key Performance Factors of Shared Memory MapReduce

2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS), pp. 1306–1317.

By: D. Tiwari n & Y. Solihin n

Source: Web Of Science
Added: August 6, 2018

2012 conference paper

WEST: Cloning data cache behavior using stochastic traces

International symposium on high-performance computer, 387–398.

By: G. Balakrishnan n & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2011 conference paper

Architectural framework for supporting operating system survivability

International symposium on high-performance computer, 456–465.

By: X. Jiang n & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2011 journal article

CHOP: INTEGRATING DRAM CACHES FOR CMP SERVER PLATFORMS

IEEE MICRO, 31(1), 99–108.

By: X. Jiang*, N. Madan*, L. Zhao*, M. Upton*, R. Iyer*, S. Makineni*, D. Newell, Y. Solihin n, R. Balasubramonian*

Source: Web Of Science
Added: August 6, 2018

2011 journal article

Evaluating Placement Policies for Managing Capacity Sharing in CMP Architectures with Private Caches

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(3).

By: A. Samih n, Y. Solihin n & A. Krishna

author keywords: Design; Performance; Measrument; Memory systems; chip multiprocessor; private caches; capacity sharing; placement policies; stack distance profiling; limit studies; QoS
Source: Web Of Science
Added: August 6, 2018

2011 conference paper

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

International symposium on high-performance computer, 99–110.

By: S. Lee n, D. Tiwari n, S. Yan n & J. Tuck n

Source: NC State University Libraries
Added: August 6, 2018

2010 chapter

An Analysis of Secure Processor Architectures

In Transactions on Computational Science VII (pp. 101–121).

By: S. Chhabra n, Y. Solihin n, R. Lal* & M. Hoekstra*

Source: Crossref
Added: August 28, 2020

2010 conference paper

CHOP: Adaptive filter-based DRAM caching for CMP server platforms

International symposium on high-performance computer, 233–244.

By: X. Jiang n, N. Madan*, L. Zhao*, M. Upton*, R. Iyer*, S. Makineni*, D. Newell*, Y. Solihin n, R. Balasubramonian*

Source: NC State University Libraries
Added: August 6, 2018

2010 chapter

Green Secure Processors: Towards Power-Efficient Secure Processor Design

In Transactions on Computational Science X (pp. 329–351).

By: S. Chhabra n & Y. Solihin n

Source: Crossref
Added: August 28, 2020

2010 conference paper

MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management

International Parallel and Distributed Processing Symposium.

By: D. Tiwari n, J. Tuck n & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2010 journal article

Quality of Service Shared Cache Management in Chip Multiprocessor Architecture

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(3).

By: F. Guo*, Y. Solihin n, L. Zhao* & R. Iyer*

author keywords: Design; Performance; Cache; chip multi-processors; CMP; multicore architecture; quality of service; QoS; performance; resource stealing
Source: Web Of Science
Added: August 6, 2018

2010 conference paper

Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance

International symposium on high-performance computer, 57–68.

By: F. Liu n, X. Jiang n & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2010 journal article

Understanding the Behavior and Implications of Context Switch Misses

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(4).

By: F. Liu n & Y. Solihin n

author keywords: Algorithms; Design; Experimentation; Performance; Context switch misses; stack distance profiling; analytical model; prefetching
Source: Web Of Science
Added: August 6, 2018

2009 article

Architecture Support for Improving Bulk Memory Copying and Initialization Performance

18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 169-+.

By: X. Jiang n, Y. Solihin n, L. Zhao* & R. Iyer*

author keywords: memory copying; memory initialization; cache affinity; cache neutral; early retirement
Source: Web Of Science
Added: August 6, 2018

2009 book

Fundamentals of parallel computer architecture multichip and multicore systems

[United States?]: Solihin Pub.

By: Y. Solihin

Source: NC State University Libraries
Added: August 6, 2018

2009 journal article

MemTracker: An Accelerator for Memory Debugging and Monitoring

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 6(2).

By: G. Venkataramani*, I. Doudalis*, Y. Solihin n & M. Prvulovic*

author keywords: Design; Performance; Reliability; Accelerator; memory access monitoring; debugging
Source: Web Of Science
Added: August 6, 2018

2009 conference paper

Memory Management Thread for Heap Allocation Intensive Applications

Workshop on Memory Performance: Dealing with Applications, Systems Architecture.

By: D. Tiwari n, S. Lee n, J. Tuck n & Y. Solihin n

Source: NC State University Libraries
Added: August 6, 2018

2009 journal article

Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 20(9), 1309–1324.

By: J. Lee*, C. Jung*, D. Lim* & Y. Solihin n

author keywords: Helper thread; prefetching; chip multiprocessors; processing-in-memory system
Source: Web Of Science
Added: August 6, 2018

2008 journal article

Counter-based cache replacement and bypassing algorithms

IEEE TRANSACTIONS ON COMPUTERS, 57(4), 433–447.

By: M. Kharbutli* & Y. Solihin n

author keywords: caches; counter-based algorithms; cache replacement algorithms; cache bypassing; cache misses
Source: Web Of Science
Added: August 6, 2018

2008 book

Fundamentals of parallel computer architecture

[United States?]: Solihin Pub.

By: Y. Solihin

Source: NC State University Libraries
Added: August 6, 2018

2008 article

Making Secure Processors OS- and Performance-Friendly

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, Vol. 5.

By: S. Chhabra n, B. Rogers n, Y. Solihin n & M. Prvulovic*

author keywords: Security; Performance; Design; Secure processor architectures; memory encryption; memory integrity verification; virtualization
Source: Web Of Science
Added: August 6, 2018

2006 article

HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, Vol. 50, pp. 261–275.

By: R. Shetty*, M. Kharbutli n, Y. Solihin n & M. Prvulovic*

Source: Web Of Science
Added: August 6, 2018

2005 journal article

Eliminating conflict misses using prime number-based cache indexing

IEEE TRANSACTIONS ON COMPUTERS, 54(5), 573–586.

By: M. Kharbutli n, Y. Solihin n & J. Lee*

author keywords: cache hashing; cache indexing; prime modulo; odd-multiplier displacement; conflict misses
Source: Web Of Science
Added: August 6, 2018

2003 journal article

Correlation prefetching with a user-level memory thread

IEEE Transactions on Parallel and Distributed Systems, 14(6), 563–580.

By: Y. Solihin*, J. Lee & J. Torrellas*

Source: NC State University Libraries
Added: August 6, 2018