Yan Solihin

Seeds of SEED: New Security Challenges for Persistent Memory

2021 INTERNATIONAL SYMPOSIUM ON SECURE AND PRIVATE EXECUTION ENVIRONMENT DESIGN (SEED 2021), pp. 83–88.

Hardware-Based Domain Virtualization for Intra-Process Isolation of Persistent Memory Objects

2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), pp. 680–692.

Compiler-support for Critical Data Persistence in NVM

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(4).

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2).

Exploring Memory Persistency Models for GPUs

28th International Conference on Parallel Architectures and Compilation Techniques (PACT), 310–322.

Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique

2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 439–451.

Scheduling Page Table Walks for Irregular GPU Applications

2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 180–192.

Clone morphing: Creating new workload behavior from existing applications

Ieee international symposium on performance analysis of systems and, 97–107.

Hiding the Long Latency of Persist Barriers Using Speculative Execution

44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 175–186.

ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories

44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 107–119.

Significant and sustaining elevation of blood oxygen induced by Chinese cupping therapy as assessed by near-infrared spectroscopy

BIOMEDICAL OPTICS EXPRESS, 8(1), 223–229.

Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache

MEMSYS 2016: PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MEMORY SYSTEMS, pp. 191–203.

Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers

Awad, A., Manadhata, P., Haber, S., Solihin, Y., & Horne, W. (2016, April). ACM SIGPLAN NOTICES, Vol. 51, pp. 263–276.

Silent shredder: Zero-cost shredding for secure non-volatile main memory controllers

Operating Systems Review, 50(2), 263–276.

Emulating cache organizations on real hardware using performance cloning

Ieee international symposium on performance analysis of systems and, 298–307.

MeToo: Stochastic Modeling of Memory Traffic Timing Behavior

2015 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION (PACT), pp. 457–467.

Non-volatile memory host controller interface performance analysis in high-performance I/O systems

Ieee international symposium on performance analysis of systems and, 145–154.

Collaborative Memories in Clusters: Opportunities and Challenges

In Transactions on Computational Science XXII (pp. 17–41).

STM : Cloning the spatial and temporal memory access behavior

International symposium on high-performance computer, 237–247.

Modeling and Analyzing Key Performance Factors of Shared Memory MapReduce

2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS), pp. 1306–1317.

WEST: Cloning data cache behavior using stochastic traces

International symposium on high-performance computer, 387–398.

Architectural framework for supporting operating system survivability

International symposium on high-performance computer, 456–465.

CHOP: INTEGRATING DRAM CACHES FOR CMP SERVER PLATFORMS

IEEE MICRO, 31(1), 99–108.

Evaluating Placement Policies for Managing Capacity Sharing in CMP Architectures with Private Caches

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(3).

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

International symposium on high-performance computer, 99–110.

An Analysis of Secure Processor Architectures

In Transactions on Computational Science VII (pp. 101–121).

CHOP: Adaptive filter-based DRAM caching for CMP server platforms

International symposium on high-performance computer, 233–244.

Green Secure Processors: Towards Power-Efficient Secure Processor Design

In Transactions on Computational Science X (pp. 329–351).

MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management

International Parallel and Distributed Processing Symposium.

Quality of Service Shared Cache Management in Chip Multiprocessor Architecture

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(3).

Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance

International symposium on high-performance computer, 57–68.

Understanding the Behavior and Implications of Context Switch Misses

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(4).

Architecture Support for Improving Bulk Memory Copying and Initialization Performance

18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 169-+.

Fundamentals of parallel computer architecture multichip and multicore systems

[United States?]: Solihin Pub.

MemTracker: An Accelerator for Memory Debugging and Monitoring

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 6(2).

Memory Management Thread for Heap Allocation Intensive Applications

Workshop on Memory Performance: Dealing with Applications, Systems Architecture.

Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 20(9), 1309–1324.

Counter-based cache replacement and bypassing algorithms

IEEE TRANSACTIONS ON COMPUTERS, 57(4), 433–447.

Fundamentals of parallel computer architecture

[United States?]: Solihin Pub.

Making Secure Processors OS- and Performance-Friendly

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, Vol. 5.

HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, Vol. 50, pp. 261–275.

Eliminating conflict misses using prime number-based cache indexing

IEEE TRANSACTIONS ON COMPUTERS, 54(5), 573–586.

Correlation prefetching with a user-level memory thread

IEEE Transactions on Parallel and Distributed Systems, 14(6), 563–580.