Yan Solihin

Yudha, A. W. B., Meyer, J., Yuan, S., Zhou, H., & Solihin, Y. (2022). LITE: A Low-Cost Practical Inter-Operable GPU TEE. PROCEEDINGS OF THE 36TH ACM INTERNATIONAL CONFERENCE ON SUPERCOMPUTING, ICS 2022. https://doi.org/10.1145/3524059.3532361

Ul Mustafa, N., Xu, Y., Shen, X., & Solihin, Y. (2021). Seeds of SEED: New Security Challenges for Persistent Memory. 2021 INTERNATIONAL SYMPOSIUM ON SECURE AND PRIVATE EXECUTION ENVIRONMENT DESIGN (SEED 2021), pp. 83–88. https://doi.org/10.1109/SEED51797.2021.00020

Xu, Y., Ye, C. C., Solihin, Y., & Shen, X. (2020). Hardware-Based Domain Virtualization for Intra-Process Isolation of Persistent Memory Objects. 2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), pp. 680–692. https://doi.org/10.1109/ISCA45697.2020.00062

Elkhouly, R., Alshboul, M., Hayashi, A., Solihin, Y., & Kimura, K. (2019). Compiler-support for Critical Data Persistence in NVM. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(4). https://doi.org/10.1145/3371236

Alshboul, M., Elnawawy, H., Elkhouly, R., Kimura, K., Tuck, J., & Solihin, Y. (2019). Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 16(2). https://doi.org/10.1145/3323091

Lin, Z., Alshboul, M., Solihin, Y., & Zhou, H. (2019). Exploring Memory Persistency Models for GPUs. 28th International Conference on Parallel Architectures and Compilation Techniques (PACT), 310–322. https://doi.org/10.1109/PACT.2019.00032

Alshboul, M., Tuck, J., & Solihin, Y. (2018). Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique. 2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 439–451. https://doi.org/10.1109/ISCA.2018.00044

Shin, S., Cox, G., Oskin, M., Loh, G. H., Solihin, Y., Bhattacharjee, A., & Basu, A. (2018). Scheduling Page Table Walks for Irregular GPU Applications. 2018 ACM/IEEE 45TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), pp. 180–192. https://doi.org/10.1109/ISCA.2018.00025

Wang, Y. P., Awad, A., & Solihin, Y. (2017). Clone morphing: Creating new workload behavior from existing applications. Ieee international symposium on performance analysis of systems and, 97–107. https://doi.org/10.1109/ispass.2017.7975274

Shin, S., Tuck, J., & Solihin, Y. (2017). Hiding the Long Latency of Persist Barriers Using Speculative Execution. 44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 175–186. https://doi.org/10.1145/3079856.3080240

Awad, A., Wang, Y., Shands, D., & Solihin, Y. (2017). ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories. 44TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2017), pp. 107–119. https://doi.org/10.1145/3079856.3080230

Li, T., Li, Y., Lin, Y., & Li, K. (2017). Significant and sustaining elevation of blood oxygen induced by Chinese cupping therapy as assessed by near-infrared spectroscopy. BIOMEDICAL OPTICS EXPRESS, 8(1), 223–229. https://doi.org/10.1364/boe.8.000223

Shin, S., Kim, S., & Solihin, Y. (2016). Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache. MEMSYS 2016: PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MEMORY SYSTEMS, pp. 191–203. https://doi.org/10.1145/2989081.2989096

Awad, A., Manadhata, P., Haber, S., Solihin, Y., & Horne, W. (2016, April). Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers. ACM SIGPLAN NOTICES, Vol. 51, pp. 263–276. https://doi.org/10.1145/2954679.2872377

Awad, A., Manadhata, P., Haber, S., Solihin, Y., & Horne, W. (2016). Silent shredder: Zero-cost shredding for secure non-volatile main memory controllers. Operating Systems Review, 50(2), 263–276. https://doi.org/10.1145/2954680.2872377

Wang, Y. P., & Solihin, Y. (2015). Emulating cache organizations on real hardware using performance cloning. Ieee international symposium on performance analysis of systems and, 298–307. https://doi.org/10.1109/ispass.2015.7095815

Wang, Y., Solihin, Y., & Balakrishnan, G. (2015). MeToo: Stochastic Modeling of Memory Traffic Timing Behavior. 2015 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION (PACT), pp. 457–467. https://doi.org/10.1109/pact.2015.36

Awad, A., Kettering, B., & Solihin, Y. (2015). Non-volatile memory host controller interface performance analysis in high-performance I/O systems. Ieee international symposium on performance analysis of systems and, 145–154. https://doi.org/10.1109/ispass.2015.7095793

Samih, A., Wang, R., Maciocco, C., Kharbutli, M., & Solihin, Y. (2014). Collaborative Memories in Clusters: Opportunities and Challenges. In Transactions on Computational Science XXII (pp. 17–41). https://doi.org/10.1007/978-3-642-54212-1_2

Awad, A., & Solihin, Y. (2014). STM : Cloning the spatial and temporal memory access behavior. International symposium on high-performance computer, 237–247. https://doi.org/10.1109/hpca.2014.6835935

Tiwari, D., & Solihin, Y. (2012). Modeling and Analyzing Key Performance Factors of Shared Memory MapReduce. 2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS), pp. 1306–1317. https://doi.org/10.1109/ipdps.2012.119

Balakrishnan, G., & Solihin, Y. (2012). WEST: Cloning data cache behavior using stochastic traces. International symposium on high-performance computer, 387–398. https://doi.org/10.1109/hpca.2012.6169042

Jiang, X. W., & Solihin, Y. (2011). Architectural framework for supporting operating system survivability. International symposium on high-performance computer, 456–465. https://doi.org/10.1109/hpca.2011.5749751

Jiang, X., Madan, N., Zhao, L., Upton, M., Iyer, R., Makineni, S., … Balasubramonian, R. (2011). CHOP: INTEGRATING DRAM CACHES FOR CMP SERVER PLATFORMS. IEEE MICRO, 31(1), 99–108. https://doi.org/10.1109/mm.2010.100

Samih, A., Solihin, Y., & Krishna, A. (2011). Evaluating Placement Policies for Managing Capacity Sharing in CMP Architectures with Private Caches. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(3). https://doi.org/10.1145/2019608.2019614

Lee, S., Tiwari, D., Yan, S. H., & Tuck, J. (2011). HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor. International symposium on high-performance computer, 99–110. https://doi.org/10.1109/hpca.2011.5749720

Chhabra, S., Solihin, Y., Lal, R., & Hoekstra, M. (2010). An Analysis of Secure Processor Architectures. In Transactions on Computational Science VII (pp. 101–121). https://doi.org/10.1007/978-3-642-11389-5_6

Jiang, X. W., Madan, N., Zhao, L., Upton, M., Iyer, R., Makineni, S., … Balasubramonian, R. (2010). CHOP: Adaptive filter-based DRAM caching for CMP server platforms. International symposium on high-performance computer, 233–244. https://doi.org/10.1109/hpca.2010.5416642

Chhabra, S., & Solihin, Y. (2010). Green Secure Processors: Towards Power-Efficient Secure Processor Design. In Transactions on Computational Science X (pp. 329–351). https://doi.org/10.1007/978-3-642-17499-5_13

Tiwari, D., Tuck, J., & Solihin, Y. (2010). MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management. International Parallel and Distributed Processing Symposium. https://doi.org/10.1109/ipdps.2010.5470428

Guo, F., Solihin, Y., Zhao, L., & Iyer, R. (2010). Quality of Service Shared Cache Management in Chip Multiprocessor Architecture. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(3). https://doi.org/10.1145/1880037.1880039

Liu, F., Jiang, X. W., & Solihin, Y. (2010). Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance. International symposium on high-performance computer, 57–68. https://doi.org/10.1109/hpca.2010.5416655

Liu, F., & Solihin, Y. (2010). Understanding the Behavior and Implications of Context Switch Misses. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(4). https://doi.org/10.1145/1880043.1880048

Jiang, X., Solihin, Y., Zhao, L., & Iyer, R. (2009). Architecture Support for Improving Bulk Memory Copying and Initialization Performance. 18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 169-+. https://doi.org/10.1109/pact.2009.31

Solihin, Y. (2009). Fundamentals of parallel computer architecture multichip and multicore systems. [United States?]: Solihin Pub.

Venkataramani, G., Doudalis, I., Solihin, Y., & Prvulovic, M. (2009). MemTracker: An Accelerator for Memory Debugging and Monitoring. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 6(2). https://doi.org/10.1145/1543753.1543754

Tiwari, D., Lee, S., Tuck, J., & Solihin, Y. (2009). Memory Management Thread for Heap Allocation Intensive Applications. Workshop on Memory Performance: Dealing with Applications, Systems Architecture. https://doi.org/10.1145/1621960.1621967

Lee, J., Jung, C., Lim, D., & Solihin, Y. (2009). Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 20(9), 1309–1324. https://doi.org/10.1109/TPDS.2008.224

Kharbutli, M., & Solihin, Y. (2008). Counter-based cache replacement and bypassing algorithms. IEEE TRANSACTIONS ON COMPUTERS, 57(4), 433–447. https://doi.org/10.1109/TC.2007.70816

Solihin, Y. (2008). Fundamentals of parallel computer architecture. [United States?]: Solihin Pub.

Chhabra, S., Rogers, B., Solihin, Y., & Prvulovic, M. (2008). Making Secure Processors OS- and Performance-Friendly. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, Vol. 5. https://doi.org/10.1145/1498690.1498691

Shetty, R., Kharbutli, M., Solihin, Y., & Prvulovic, M. (2006). HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection. IBM JOURNAL OF RESEARCH AND DEVELOPMENT, Vol. 50, pp. 261–275. https://doi.org/10.1147/rd.502.0261

Kharbutli, M., Solihin, Y., & Lee, J. (2005). Eliminating conflict misses using prime number-based cache indexing. IEEE TRANSACTIONS ON COMPUTERS, 54(5), 573–586. https://doi.org/10.1109/TC.2005.79

Solihin, Y., Lee, J., & Torrellas, J. (2003). Correlation prefetching with a user-level memory thread. IEEE Transactions on Parallel and Distributed Systems, 14(6), 563–580. https://doi.org/10.1109/tpds.2003.1206504