@inproceedings{priyadarshi_davis_franzon_2014, title={Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC}, ISBN={9781479921539}, url={http://dx.doi.org/10.1109/icicdt.2014.6838612}, DOI={10.1109/icicdt.2014.6838612}, abstractNote={Three dimensional integration technologies offer significant potential to improve performance, performance per unit power and integration density. However, increased power density and thermal resistances leading to higher on-chip temperature is imposing several implementation challenges and restricting widespread adaptation of this technology. This necessitates the need for CAD flows and tools facilitating early thermal evaluation of possible 3D design choices and thermal management techniques. This paper presents a CAD flow and associated framework called Pathfinder3D, which facilitates physically-aware system-level thermal simulation of 3DICs. Usage of Pathfinder3D is shown using a case study comparing thermal profiles of 2D and three 3D implementations of a quadcore chip multiprocessor.}, booktitle={2014 IEEE International Conference on IC Design & Technology}, publisher={IEEE}, author={Priyadarshi, Shivam and Davis, W. Rhett and Franzon, Paul D.}, year={2014}, month={May} }
 @article{priyadarshi_davis_steer_franzon_2014, title={Thermal Pathfinding for 3-D ICs}, volume={4}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2014.2321005}, abstractNote={System architects traditionally use high-level models of component blocks to predict trends for various design metrics. However, with continually increasing design complexity and a confusing array of manufacturing choices, system-level design decisions cannot be made without considering physical-level details. This effect is more pronounced for 3-D integrated circuits (ICs) because it provides a plethora of physical-level design choices, such as the number of stacking layers and the type of 3-D bonding method, along with the choices provided by 2-D ICs. Thus, it is necessary for system-level flows to predict the complex interactions among system performance, power, temperature, floorplanning, process technology, computer architecture, and software/workloads. This is often called pathfinding. This paper presents a pathfinding flow that integrates SystemC transaction-level electrical and dynamic thermal simulations. The goal of this flow is to pass complex physical constraints to system architects in a convenient form. The applicability of the proposed flow is shown using an example stacking of two processor cores and L2 cache in two-tier 3-D stack.}, number={7}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Priyadarshi, Shivam and Davis, W. Rhett and Steer, Michael B. and Franzon, Paul D.}, year={2014}, month={Jul}, pages={1159–1168} }
 @inproceedings{franzon_priyadarshi_lipa_davis_thorolfsson_2013, title={Exploring early design tradeoffs in 3DIC}, DOI={10.1109/iscas.2013.6571901}, abstractNote={This The key to gaining substantial benefit from the use of 3DIC technology is to create 3D specific designs that do more than recast a 2D optimal design into the third dimension. This paper explores some of the approaches to creating 3D specific designs and the CAD tools that can help in that exploration. The power advantages of 3D design are illustrated in details. Results from different partitioning approaches (function, modular and circuit) are presented, together with early results from a thermal pathfinding tool.}, booktitle={2013 IEEE International Symposium on Circuits and Systems (ISCAS)}, author={Franzon, P. D. and Priyadarshi, S. and Lipa, S. and Davis, W. R. and Thorolfsson, T.}, year={2013}, pages={545–549} }
 @inproceedings{priyadarshi_choudhary_dwiel_upreti_rotenberg_davis_franzon_2013, title={Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors}, DOI={10.1109/isqed.2013.6523582}, abstractNote={Timing the transition of a processor design to a new technology poses a provocative tradeoff. On the one hand, transitioning as early as possible offers a significant competitive advantage, by bringing improved designs to market early. On the other hand, an aggressive strategy may prove to be unprofitable, due to the low manufacturing yield of a technology that has not had time to mature. We propose exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP). First, 3D integration facilitates a technology alloy. The CMP is split across two dies, one fabricated in the old technology and the other in the new technology. The alloy derives benefit from the new technology while limiting cost exposure. Second, to compensate for lower efficiency of old-technology cores, we exploit application and microarchitectural heterogeneity: applications which gain less from technology scaling are scheduled on old-technology cores, moreover, these cores are retuned to optimize this class of application. For a defect density ratio of 200 between 45nm and 65nm, Hetero2 3D gives 3.6× and 1.5× higher efficiency/cost compared to 2D and 3D homogeneous implementations, respectively, with only 6.5% degradation in efficiency. We also present a sensitivity analysis by sweeping the defect density ratio. The analysis reveals the defect density break-even points, where homogeneous 2D and 3D designs in 45nm achieve the same efficiency/cost as Hetero2 3D, marking significant points in the maturing of the technology.}, booktitle={Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013)}, author={Priyadarshi, S. and Choudhary, N. and Dwiel, B. and Upreti, A. and Rotenberg, E. and Davis, R. and Franzon, P.}, year={2013}, pages={1–7} }
 @article{harris_priyadarshi_melamed_ortega_manohar_dooley_kriplani_davis_franzon_steer_et al._2012, title={A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits}, volume={2}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2011.2178414}, abstractNote={A transient electrothermal simulation of a 3-D integrated circuit (3DIC) is reported that uses dynamic modeling of the thermal network and hierarchical electrothermal simulation. This is a practical alternative to full transistor electrothermal simulations that are computationally prohibitive. Simulations are compared to measurements for a token-generating asynchronous 3DIC clocking at a maximum frequency of 1 GHz. The electrical network is based on computationally efficient electrothermal macromodels of standard and custom cells. These are linked in a physically consistent manner with a detailed thermal network extracted from an OpenAccess layout file. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles.}, number={4}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Harris, T.R. and Priyadarshi, S. and Melamed, S. and Ortega, C. and Manohar, R. and Dooley, S.R. and Kriplani, N.M. and Davis, W.R. and Franzon, Paul and Steer, M.B. and et al.}, year={2012}, month={Apr}, pages={660–667} }
 @article{melamed_thorolfsson_harris_priyadarshi_franzon_steer_davis_2012, title={Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring}, volume={31}, DOI={10.1109/tcad.2011.2180384}, abstractNote={The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity “far response” in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.}, number={5}, journal={IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems}, author={Melamed, S. and Thorolfsson, T. and Harris, T. R. and Priyadarshi, S. and Franzon, Paul and Steer, M. B. and Davis, W. R.}, year={2012}, pages={676–689} }
 @article{priyadarshi_saunders_kriplani_demircioglu_davis_franzon_steer_2012, title={Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning}, volume={31}, ISSN={["1937-4151"]}, DOI={10.1109/tcad.2012.2201156}, abstractNote={A parallel transient simulation technique for multiphysics circuits is presented. The technique develops partitions utilizing the inherent delay present within a circuit and between physical domains. A state-variable-based circuit delay element is presented, which implements the coupling between two spatially or temporally isolated circuit partitions. A parallel delay-based iterative approach for interfacing delay-partitioned subcircuits is applied, which achieves the reasonable accuracy of nonparallel circuit simulation if both incorporate the same interblock delay. The partitioned subcircuits are distributed to different cores of a shared-memory multicore processor and solved in parallel. A multithreaded implementation of the methodology using OpenMP is presented. Examples showing superlinear speedup compared to unpartitioned single-core simulation using the direct method are presented. This paper also discusses the impact of load balancing and absolute delay on simulation speedup.}, number={10}, journal={IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS}, author={Priyadarshi, Shivam and Saunders, Christopher S. and Kriplani, Nikhil M. and Demircioglu, Harun and Davis, W. Rhett and Franzon, Paul D. and Steer, Michael B.}, year={2012}, month={Oct}, pages={1522–1535} }
 @article{schinke_priyadarshi_pitts_di spigna_franzon_2011, title={SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation}, volume={5}, ISSN={["1751-858X"]}, DOI={10.1049/iet-cds.2010.0410}, abstractNote={The majority of nanocrystal floating gate research has been done at the device level. Circuit-level research is still in its early stages because of the lack of a physical device model appropriate for circuit simulations. In this study, a comprehensive and accurate SPICE-compatible physical equation-based model of nanocrystal floating gate devices is developed based on uniform direct tunnelling and Fowler-Nordheim tunnelling. The main contribution is a Verilog-A module that captures the physical behaviours of programming and erasing the device. A predictive NMOS model is then used for modelling the conduction channel to determine the behavioural I - V characteristics. The proposed model uses only explicit formulae resulting in fast computation appropriate for circuit simulation and can be used in any SPICE simulator supporting Verilog-A. It interacts dynamically with the rest of the circuit and includes charge leakage which enables power consumption analysis. The simulation results of the proposed model fit well to experimental results of various fabricated devices. Additionally, it is verified in HSPICE, demonstrating a significant speedup and good agreement with a numerical device simulator. This study is important in bridging the gap between device- and circuit-level research.}, number={6}, journal={IET CIRCUITS DEVICES & SYSTEMS}, author={Schinke, D. and Priyadarshi, S. and Pitts, W. Shepherd and Di Spigna, N. and Franzon, P.}, year={2011}, month={Nov}, pages={477–483} }