@article{das_satpathy_bhattacharya_veliadis_deshpande_bhargava_2023, title={Determination of Parameters of Symmetrical Six-Phase Permanent Magnet Synchronous Machines}, DOI={10.1109/IEMDC55163.2023.10238906}, abstractNote={This paper presents offline methods to determine different parameters of Symmetrical Six-Phase (SSP) Permanent Magnet Synchronous Machines (PMSMs). Accurate estimations of different parameters are crucial for proper machine modeling, control, and performance estimations. This paper discusses two offline methods to accurately determine different inductances and the stator resistance of SSP-PMSMs using a single-phase AC source. A method to calculate the Permanent Magnet (PM) flux linkage is also discussed. Machine parameters of a high-speed, low-inductance SSP-PMSM are determined using both methods. The determined parameters are compared with Finite Element Analysis (FEA)-based simulation results and the results are presented in this paper.}, journal={2023 IEEE INTERNATIONAL ELECTRIC MACHINES & DRIVES CONFERENCE, IEMDC}, author={Das, Partha Pratim and Satpathy, Subhransu and Bhattacharya, Subhashish and Veliadis, Victor and Deshpande, Uday and Bhargava, Brij}, year={2023} }
 @article{satpathy_das_bhattacharya_veliadis_2022, title={A New Switching Strategy for a GaN-based Three-Level Active Neutral Point Clamped Converter}, ISSN={["2329-3721"]}, DOI={10.1109/ECCE50734.2022.9947699}, abstractNote={This paper investigates a suitable switching strategy for a GaN-based three-level active neutral point clamped (3L-ANPC) converter. The 3L-ANPC operation is considered at 800V DC bus with the use of 650V GaN devices. The different switching modes for obtaining the zero state result in short-loop and long-loop commutations. A parallel operation of zero states termed full-mode is preferable for reducing conduction losses. However, this results in a multi-loop commutation producing high voltage stress across the inner devices. This paper proposes a modified full-mode switching strategy to mitigate this issue by a timed switching sequence involving clamping devices. The proposed switching mode involves active switching of the clamping device in 3L-ANPC for coupling and decoupling the long loop path. The commutation process for the proposed switching mode is explained in detail in this paper. Simulation results are presented using the device Spice model and parasitic inductances of a designed 3L-ANPC phase leg. The voltage stress and loss results determined from simulation results are compared with existing switching modes. A three-level double pulse test circuit is presented, and experimental test results are provided for the proposed switching mode.}, journal={2022 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Satpathy, Subhransu and Das, Partha Pratim and Bhattacharya, Subhashish and Veliadis, Victor}, year={2022} }
 @article{das_satpathy_bhattacharya_veliadis_2022, title={Design Considerations of Multi-Phase Multilevel Inverters for High-Power Density Traction Drive Applications}, DOI={10.1109/ITEC53557.2022.9813937}, abstractNote={This paper presents the effect of multi-phase machines in Three-Level (3L) Active Neutral-Point Clamped (ANPC) inverter design for high-speed traction drive applications. In this work, GaN-based 3L-ANPC inverters are considered to drive high-speed Permanent Magnet Synchronous Machines (PMSMs) with an 800V DC bus. Two different analytical models are developed to calculate the DC bus capacitor and dv/dt filter requirements of the 3L-ANPC inverters. Using the analytical models, the requirement of the DC bus capacitor and dv/dt filter sizes are compared for driving three-phase, six-phase symmetrical, and asymmetrical PMSMs. Another model is developed from experimental Double Pulse Test (DPT) data to calculate the heat sink size requirements for driving the three types of PMSMs mentioned above. A discussion on the Common Mode Voltage (CMV) is also provided. Finally, a comparison is made in terms of DC bus capacitor, dv/dt filter, heat sink size requirements, and common-mode voltages for the three types of drives. The analytical models are verified in simulation, and the results are presented in this paper.}, journal={2022 IEEE/AIAA TRANSPORTATION ELECTRIFICATION CONFERENCE AND ELECTRIC AIRCRAFT TECHNOLOGIES SYMPOSIUM (ITEC+EATS 2022)}, author={Das, Partha Pratim and Satpathy, Subhransu and Bhattacharya, Subhashish and Veliadis, Victor}, year={2022}, pages={23–30} }
 @article{das_satpathy_bhattacharya_veliadis_2022, title={Generalized Control Technique for Three-Level Inverter Fed Six-Phase Permanent Magnet Synchronous Machines Under Fault Conditions}, ISSN={["2329-3721"]}, DOI={10.1109/ECCE50734.2022.9947672}, abstractNote={This paper presents a control technique of a GaN-based Three-Level (3L) Active Neutral Point Clamped (ANPC) inverter fed high-speed six-phase Permanent Magnet Synchronous Machine (PMSM) under both Open Circuit Fault (OCF) and Short Circuit Fault (SCF) conditions. The loss of one or more phases due to OCF or SCF in PMSMs can generate a high torque ripple. A high torque ripple can disrupt the operation of electric drives and even bring the drive to a standstill. Smooth operation under any fault conditions is becoming necessary to increase the reliability of the electric drives. This paper discusses an optimization method that calculates the operating points in different fault conditions while maximizing the torque without exceeding the rated line current rating of the inverter/ motor. The optimization method also provides the torque limit in post-fault conditions without compromising the speed for both one and two isolated neutral point configurations. The post-fault operating points are implemented using a control technique that can be achieved seamlessly from the state-of-the-art vector control method. The proposed control technique is verified in simulation, and the results are presented in this paper.}, journal={2022 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Das, Partha Pratim and Satpathy, Subhransu and Bhattacharya, Subhashish and Veliadis, Victor}, year={2022} }
 @article{das_satpathy_bhattacharya_2021, title={An Improved PWM Method for Minimum Common-Mode Circulating Current Operation of Six Phase Three Level Inverter}, ISSN={["1048-2334"]}, DOI={10.1109/APEC42165.2021.9487259}, abstractNote={This paper presents a simple Pulse Width Modulation (PWM) technique to reduce the common-mode circulating current of a six-phase three-level inverter. Six-phase inverters generally suffer high common-mode circulating current when space vector PWM (SVPWM) or min-max method is used with a common neutral point. For common-mode circulating current reduction, Phase Disposition (PD) PWM with a compromised third harmonics injection method is proposed in this work. The selected third harmonics injection method removes the low-frequency common-mode circulating current. The absence of low frequency circulating current improves the THD of the load currents. Finally, the proposed method is tested in PLECS simulation with a 75KW system, and results are presented here.}, journal={2021 THIRTY-SIXTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2021)}, author={Das, Partha Pratim and Satpathy, Subhransu and Bhattacharya, Subhashish}, year={2021}, pages={1070–1077} }
 @article{das_satpathy_shah_bhattacharya_veliadis_2021, title={Paralleling of Four 650V/60A GaN HEMTs for High Power Traction Drive Applications}, ISSN={["2329-3721"]}, DOI={10.1109/ECCE47101.2021.9595766}, abstractNote={This paper presents design considerations and experimental verification of a GaN-based half-bridge 650V/160A power converter block with four parallel 650V/60AGaN High Electron Mobility Transistors (HEMTs) for high-power traction drive applications. Paralleling of semiconductor devices is common for high power density applications. However, paralleling more than two GaN devices is challenging as parasitic inductances and resistances need to be well matched for all the devices. In addition, the DC loop inductances must be minimized to reduce the device voltage overshoot during turn-off. The gate loop inductances must also be matched and minimized to improve current sharing and reduce gate voltage oscillations. A detailed design method of a half-bridge with four parallel devices is discussed in this paper for matching gate and DC loop inductances. A half-bridge test circuit with four parallel enhancement-mode GaN (e-GaN) HEMTs is designed following the design method. The inductance matchings are verified with a detailed Q3D simulation. Finally, Double Pulse Test (DPT) results at 400V/160A are presented in this paper to demonstrate the half-bridge converter block’s current sharing and loss distributions.}, journal={2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Das, Partha Pratim and Satpathy, Subhransu and Shah, Suyash Sushilkumar and Bhattacharya, Subhashish and Veliadis, Victor}, year={2021}, pages={5269–5276} }
 @article{satpathy_das_bhattacharya_2021, title={Study of Switching Transients based on dv/dt and di/dt for a GaN-based Two-Level Pole}, ISSN={["2150-6078"]}, DOI={10.1109/ECCE-Asia49820.2021.9479426}, abstractNote={The faster switching transients of GaN devices lead to extremely low switching loss. This is a key feature that makes GaN devices a potential candidate for power converters driving high speed electric machines. The switching transients occur in tens of nanoseconds leading to very high dv/dt and di/dt. This leads to several challenges for both power converter as well as motor load. Switching device voltage overshoot and insulation stress for motors are key concerns among them. A practical operation of power converter needs to consider minimizing the losses while addressing these challenges. Analytical models for switching transient help in investigating the mitigation of these challenges from the gate drive side. This paper presents a systematic modeling approach that divides the turn-on and turn-off transient intervals of a GaN-based two-level pole into sub-intervals responsible for di/dt and dv/dt. The switching loss contribution of each sub-interval and their role in transient overshoot is highlighted. Using switching device voltage overshoot and motor dv/dt as two important constraints, an optimal gate drive is then proposed, which minimizes the switching loss. Spice simulation results are presented for the proposed optimal gate drive of 650 V, 60 A GaN device operating at 400 V DC bus voltage and 40 A device current.}, journal={2021 IEEE 12TH ENERGY CONVERSION CONGRESS AND EXPOSITION - ASIA (ECCE ASIA)}, author={Satpathy, Subhransu and Das, Partha Pratim and Bhattacharya, Subhashish}, year={2021}, pages={19–25} }