@article{nigussie_pan_lipa_pitts_delacruz_franzon_2021, title={Design Benefits of Hybrid Bonding for 3D Integration}, ISSN={["2377-5726"]}, DOI={10.1109/ECTC32696.2021.00296}, abstractNote={We present electrical and thermal analyses of 3D digital designs using hybrid bonding, specifically using the design rules, and other properties, for the XPERI DBI® technology at a $\mathrm{1.6}\ \mu \mathrm{m}$ pad pitch. We also go over the advantages of hybrid bonding over thermo-compression bonding (TCB) and 2D designs. Commercial 3D physical design tools were not mature when we did this work, so we came up with a methodology that builds on 2D tools. Our design flow includes scripts for optimal assignment of bonding locations, partitioning of netlist and delay constraints, and optimization techniques that involve iterating on delay constraints. Various partitioning schemes that include targeting long nets, managing flip-flop distribution between tiers, and minimum cut partitioning using an open source tool were analyzed. Because analysis results could vary from design to design, we propose potential metrics that can be used to identify designs that may benefit from 3DIC technology. Analysis results showed that we were able to reduce routed wire length by up to 57%. Logic power and total power decreased by up to 34% and 22% respectively. Silicon area also improved by 11%.11This work was supported, in part, by Xperi. DISTRIBUTION STATE-MENT A. Approved for public release: distribution unlimited.}, journal={IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021)}, author={Nigussie, Theodros and Pan, Tse-Han and Lipa, Steve and Pitts, W. Shepherd and DeLaCruz, Javi and Franzon, Paul}, year={2021}, pages={1876–1881} }
 @article{franzon_davis_rotenberg_stevens_lipa_nigussie_pan_baker_schabel_dey_et al._2021, title={Design for 3D Stacked Circuits}, ISSN={["2380-9248"]}, DOI={10.1109/IEDM19574.2021.9720553}, abstractNote={2.5D and 3D technologies can give rise to a node equivalent of scaling due to improved connectivity. Aggressive exploitation scenarios include functional partitioning, circuit partitioning, logic on DRAM, design obfuscation and modular chiplets. Design issues that need to be addressed in pursuing such exploitations include thermal management, design for test and computer aided design.}, journal={2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)}, author={Franzon, P. and Davis, W. and Rotenberg, E. and Stevens, J. and Lipa, S. and Nigussie, T. and Pan, H. and Baker, L. and Schabel, J. and Dey, S. and et al.}, year={2021} }
 @inproceedings{nigussie_franzon, title={RDL and interposer design for DiRAM4 interfaces}, booktitle={Ieee conference on electrical performance of electronic packaging and}, author={Nigussie, T. and Franzon, P. D.}, pages={17–19} }