@article{stevens_pan_ravichandiran_franzon_2023, title={Chiplet Set For Artificial Intelligence}, ISSN={["2164-0157"]}, DOI={10.1109/3DIC57175.2023.10154953}, abstractNote={The design reuse strategy has significantly shortened the time required to create complex System on Chips (SoCs). However, when introducing new intellectual properties (IPs), the monolithic SoC methodology requires a re-run of system-level validation steps, incurring significant costs. Partitioning the design into chiplets over an interposer would mitigate these issues by consigning the IP updates to the individual chiplet. This paper presents a chipletized design used for Artificial Intelligence (AI). This design details a scalable AI chiplet set, along with Central Processing Units (CPUs). The AI chiplet set includes an Long Short Term Memory (LSTM) Application Specific Instruction Set Processor (ASIP) for accelerating inference and training and an Sparse Convolution Neural Network (SCNN) ASIP for accelerating inference through a zero-skipping technique. The CPUs control AI accelerators and handle general tasks. The accelerators and CPUs have an AXI crossbar Network on Chip (NoC) for memory and one for controlling the accelerators. This project has two phases: phase one, IP validation with an emulated interposer (No interposer, connect chiplets through back end of line (BEOL) metal layers), and phase two, connecting validated IP through an interposer. This paper focuses on phase one, which uses the United Semiconductor Japan Co. (USJC) 55 nm LP process to fabricate the design. The chiplets' clock frequencies range from 200 - 400 MHz.}, journal={2023 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE, 3DIC}, author={Stevens, Joshua A. and Pan, Tse-Han and Ravichandiran, Prasanth Prabu and Franzon, Paul D.}, year={2023} }
 @article{pan_franzon_srinivas_nagarajan_popovic_2023, title={System Aware Floorplanning for Chip-Package Co-design}, ISSN={["2165-4107"]}, DOI={10.1109/EPEPS58208.2023.10314897}, abstractNote={SoC floorplanning is crucial as it bridges the system design and the physical design of the chip. In this paper, we present a new floorplanning solution based on a novel floorplan model that more closely depicts the design challenges imposed by modern SoC system constraints. Our experimental results demonstrated that this solution is able to create floorplans with hard peripheral instances and soft rectilinear instances with zero white space while supporting system constraints on multiple design instances.}, journal={2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS}, author={Pan, Tse-Han and Franzon, Paul D. and Srinivas, Vaishnav and Nagarajan, Mahalingam and Popovic, Darko}, year={2023} }
 @article{nigussie_pan_lipa_pitts_delacruz_franzon_2021, title={Design Benefits of Hybrid Bonding for 3D Integration}, ISSN={["2377-5726"]}, DOI={10.1109/ECTC32696.2021.00296}, abstractNote={We present electrical and thermal analyses of 3D digital designs using hybrid bonding, specifically using the design rules, and other properties, for the XPERI DBI® technology at a $\mathrm{1.6}\ \mu \mathrm{m}$ pad pitch. We also go over the advantages of hybrid bonding over thermo-compression bonding (TCB) and 2D designs. Commercial 3D physical design tools were not mature when we did this work, so we came up with a methodology that builds on 2D tools. Our design flow includes scripts for optimal assignment of bonding locations, partitioning of netlist and delay constraints, and optimization techniques that involve iterating on delay constraints. Various partitioning schemes that include targeting long nets, managing flip-flop distribution between tiers, and minimum cut partitioning using an open source tool were analyzed. Because analysis results could vary from design to design, we propose potential metrics that can be used to identify designs that may benefit from 3DIC technology. Analysis results showed that we were able to reduce routed wire length by up to 57%. Logic power and total power decreased by up to 34% and 22% respectively. Silicon area also improved by 11%.11This work was supported, in part, by Xperi. DISTRIBUTION STATE-MENT A. Approved for public release: distribution unlimited.}, journal={IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021)}, author={Nigussie, Theodros and Pan, Tse-Han and Lipa, Steve and Pitts, W. Shepherd and DeLaCruz, Javi and Franzon, Paul}, year={2021}, pages={1876–1881} }