@inproceedings{franzon_priyadarshi_lipa_davis_thorolfsson_2013, title={Exploring early design tradeoffs in 3DIC}, DOI={10.1109/iscas.2013.6571901}, abstractNote={This The key to gaining substantial benefit from the use of 3DIC technology is to create 3D specific designs that do more than recast a 2D optimal design into the third dimension. This paper explores some of the approaches to creating 3D specific designs and the CAD tools that can help in that exploration. The power advantages of 3D design are illustrated in details. Results from different partitioning approaches (function, modular and circuit) are presented, together with early results from a thermal pathfinding tool.}, booktitle={2013 IEEE International Symposium on Circuits and Systems (ISCAS)}, author={Franzon, P. D. and Priyadarshi, S. and Lipa, S. and Davis, W. R. and Thorolfsson, T.}, year={2013}, pages={545–549} }
 @inproceedings{thorolfsson_lipa_franzon_2012, title={A 10.35 mW/GFlop Stacked SAR DSP unit using fine-grain partitioned 3D integration}, DOI={10.1109/cicc.2012.6330589}, abstractNote={In this paper we present a technique for implementing a fine-grain partitioned three-dimensional SAR DSP system using 3D placement of standard cells where only one of the 3D tiers is clocked to reduce clock power. We show how this technique was used to build the first fine-grain partitioned 3D integrated system to be demonstrated with silicon measurements in the literature, which is an ultra efficient floating-point synthetic aperture radar (SAR) DSP processing unit. The processing unit was fabricated in two tiers of GlobalFoundries, 1.5 V 130nm process that were 3D stacked face-to-face by Tezzaron. After fabrication the test chip was measured to consume 4.14 mW of power while running at 40 MHz operating for an operating efficiency of 10.35 mW/GFlop.}, booktitle={2012 ieee custom integrated circuits conference (cicc)}, author={Thorolfsson, T. and Lipa, S. and Franzon, Paul}, year={2012} }
 @article{moezzi-madani_thorolfsson_chiang_davis_2012, title={Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding}, volume={68}, ISSN={["1939-8115"]}, DOI={10.1007/s11265-011-0595-9}, number={2}, journal={JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY}, author={Moezzi-Madani, Nariman and Thorolfsson, Thorlindur and Chiang, Patrick and Davis, William Rhett}, year={2012}, month={Aug}, pages={171–182} }
 @article{melamed_thorolfsson_harris_priyadarshi_franzon_steer_davis_2012, title={Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring}, volume={31}, DOI={10.1109/tcad.2011.2180384}, abstractNote={The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity “far response” in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.}, number={5}, journal={IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems}, author={Melamed, S. and Thorolfsson, T. and Harris, T. R. and Priyadarshi, S. and Franzon, Paul and Steer, M. B. and Davis, W. R.}, year={2012}, pages={676–689} }
 @inproceedings{franzon_davis_thorolfsson_melamed_2011, title={3D specific systems: Design and CAD}, DOI={10.1109/ats.2011.99}, abstractNote={3D stacking and integration can provide significant system advantages. Following a brief technology review, this abstract explores application drivers, design and CAD for 3D ICs. The main 3D exploitation explored in detail is that of logic on memory. This application is explored in a specific DSP example, showing a 25% power advantage when implemented in 3D compared with 2D. Finally critical areas that need better solutions are explored. These include cost management, design planning, test management, and thermal management.}, booktitle={2011 Asian Test Symposium}, author={Franzon, P. D. and Davis, W. R. and Thorolfsson, T. and Melamed, S.}, year={2011}, pages={470–473} }
 @article{thorolfsson_moezzi-madani_franzon_2011, title={Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor}, volume={5}, ISSN={["1751-861X"]}, DOI={10.1049/iet-cdt.2009.0106}, abstractNote={In this study, the authors present a floating-point synthetic aperture radar processor that achieves a power efficiency of 18.0 mW/GFlop in simulation through the use of three-dimensional (3D) integration and reconfiguration of the data path. The reconfiguration reduces the number of arithmetic units required in every processing element (PE) from 24 down to 10. The processor uses a 3D integrated memory that reduces the memory power consumption by 70% when compared to a 2D memory. The system processes a SAR image using a two-tier 3D integrated PE, which when compared to an equivalent 2D PE decreases the power consumed in the interconnect of each PE by 15.5% and the footprint by 49.2%, and allows the PE to operate 7.1% faster in simulation. Additionally, by using 3D integration in the memory one can reduce the power consumption of the memory by 70%. Furthermore, the authors show how the 3D aspects of the processor can be realised by using 2D tools, when used in conjunction with the proposed through-silicon via assignment algorithm.}, number={3}, journal={IET COMPUTERS AND DIGITAL TECHNIQUES}, author={Thorolfsson, T. and Moezzi-Madani, N. and Franzon, P. D.}, year={2011}, month={May}, pages={198–204} }
 @inproceedings{thorolfsson_moezzi-madani_franzon_2009, title={A low power 3D integrated FFT engine using hypercube memory division}, DOI={10.1145/1594233.1594289}, abstractNote={In this paper we demonstrate a floating point FFT processor that leverages both 3D integration and a hypercube memory division scheme to reduce the power consumption of a 1024 point FFT down to 4.227 μJ. The hypercube memory division scheme lowers the energy per memory access by 59.2% while only increasing the total area required by 16.8%, while using 3D integration reduces the logic power by 5.2%. For comparison, we analyze the amount of power and wire length reduction that can be expected from 3D integration for normal digital logic circuits.}, booktitle={ISLPED 09}, author={Thorolfsson, T. and Moezzi-Madani, N. and Franzon, Paul}, year={2009}, pages={231–236} }
 @inproceedings{melamed_thorolfsson_srinivasan_cheng_franzon_davis_2009, title={Junction-level thermal extraction and simulation of 3DICs}, DOI={10.1109/3DIC.2009.5306529}, abstractNote={In 3DICs heat dissipating devices are stacked directly on top of each other leading to a higher heat density than in a comparable 2D chip. 3D integration also moves the majority of active devices further away from the heatsink. This results in a degraded thermal path which makes it more challenging to remove heat from the active devices. Gradient FireBolt was used to perform an appropriate 3D thermal analysis on a 1024-point, memory-on-logic 3DIC FFT processor for synthetic aperture radar (SAR). The chip was simulated with a spatial resolution of 80 nm, and was modeled to include the effect of each line of interconnect, as well as each via and fill structure exactly as drawn in the layout. Large isolated temperature spikes were found near groups of clock buffers at the edge of the SRAMs on the middle tier. It was found that lowering the simulation resolution and using composite thermal conductivities failed to accurately predict the location of these tentpoles.}, booktitle={2009 IEEE International Conference on 3d Systems Integration}, author={Melamed, S. and Thorolfsson, T. and Srinivasan, A. and Cheng, E. and Franzon, P. and Davis, R.}, year={2009}, pages={395–401} }
 @inproceedings{thorolfsson_melamed_charles_franzon, title={Comparative analysis of two 3D integration implementations of a SAR processor}, booktitle={2009 IEEE International Conference on 3d Systems Integration}, author={Thorolfsson, T. and Melamed, S. and Charles, G. and Franzon, P. D.}, pages={25–28} }