@article{ke_mehrotra_hopkins_2021, title={3-D Prismatic Packaging Methodologies for Wide Band Gap Power Electronics Modules}, volume={36}, ISSN={["1941-0107"]}, DOI={10.1109/TPEL.2021.3081679}, abstractNote={In a power module the parasitic inductance limits the dynamic high-frequency performance, and the area of the cooling surfaces limits the power capability. This article presents a new 3-D power electronic design methodology based on the concept of mutual inductance cancellation and multisided heat transfer. New 3-D prismatic packaging concepts are proposed for wide band gap power devices, where the devices can be mounted at acute angles to adjacent interconnects or other devices. Discussion is given on electrical and thermal path optimization in a 3-D space. To validate the 3-D prismatic packaging methodology, a 1200 V/50 A SiC half-bridge power module is fabricated and tested for electrical and thermal performance and results are compared with simulations. The power density calculated for the module is 12 kW/in3 (including heatsink) and shows a 31.3% inductance reduction compared to a 2-D planar module. Finally, design guidance suggested for utilizing prismatic structures is provided, together with suggested future work in the area. This article presents the first reported true 3-D power module.}, number={11}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Ke, Haotao and Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2021}, month={Nov}, pages={13057–13066} }
 @inproceedings{mehrotra_hopkins_2021, title={A New Cascaded SuperCascode High Voltage Power Switch}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487049}, DOI={10.1109/APEC42165.2021.9487049}, abstractNote={Medium Voltage (MV), High Current (HC) switches are growing in demand for MV applications in land, sea and air transport, fast charging, renewable energy, and a host of applications in pulsed power, e.g. solid-state protection. However, widespread adoption of commercially available MV-HC modules is limited due to retracted dynamic performance from paralleling many high voltage, low current semiconductors. The associated cost is relatively high because of low yield, and expensive material and fabrication. An alternative is series connection of Low Voltage (LV)-HC semiconductors to form a SuperCascode (SC) power switch. This paper introduces a Cascaded SuperCascode (CSC) power switch topology that scales to very high voltages (>100 kV) or applied to optimize previously reported MV SCs to achieve higher switching speed, reduced balancing network size and lower switching losses. This paper describes the design of the balancing network for optimized CSC switch switching speed, and provides simulation and test results of a 6.5 kV power switch. The switch simulated to show a 4.5x improvement in switching speed (avg of Ton and Toff), 40% reduction in switching losses, 60% net charge reduction in network capacitors (i.e. size reduction) and superior avalanche energy management for greater short circuit performance compared to other SCs. The switch was fabricated and tested showing 408 mΩ, 0.7 mA @ 4.8 kV and 23ns rise and 50ns fall in current at 4kV for 50A switching from double-pulse testing (DPT).}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2021}, month={Jun}, pages={2251–2257} }
 @article{mehrotra_hopkins_2021, title={Analytical Method to Optimize the Cascaded SuperCascode Power Switch Balancing Network}, DOI={10.1109/WiPDA49284.2021.9645114}, abstractNote={SuperCascode Power Switches (SCPS) use series-connected Low Voltage (LV)- High Current (HC) devices in a serial string to realize High Voltage (HV) – HC power switches. Cascading of SuperCascodes (CSC) is a modification of the earlier proposed SCPS concept aimed to scale the switching topology to very high (>100kV) levels or applied to optimize previously reported HV SCPSs to achieve higher switching speed, reduced balancing network size and lower switching losses. However, certain practical challenges create engineering constraints in design which will be discussed and highlighted in this paper. Firstly, for a serial string of devices, scaling the devices adds stray inductances which lead to delays in triggering serial devices, de-synchronization of triggering and unexpected overvoltages that limit scalability. This paper provides an analytical model to enable optimization through simulation and provides experimental data verifying the model.}, journal={2021 IEEE 8TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA)}, author={Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2021}, pages={107–111} }
 @article{mehrotra_ballard_hopkins_2021, title={Bidirectional Solid-State Circuit Breaker using Super Cascode for MV SST and Energy Storage Systems}, volume={10}, ISSN={2168-6777 2168-6785}, url={http://dx.doi.org/10.1109/JESTPE.2021.3081684}, DOI={10.1109/JESTPE.2021.3081684}, abstractNote={Solid-state transformers (SSTs) are developing as highly efficient interfaces in renewable energy, transport, and energy storage systems (ESSs). However, performance limitations, such as overvoltage sensitivity and fault handling capabilities, have slowed widespread adoption. Although SSTs are developing added capabilities for fault management, the required response speed and overdesign introduces added costs, particularly in protection of ultralow inductance systems, such as those sourced by ESSs. With increased use of power electronics, the power distribution systems are speeding up having shorter fault propagation delays and higher fault currents. This creates a need for alternative approaches to MV system protection. This article describes a bidirectional solid-state circuit breaker (BSSCB) based on a new SiC SuperCascode power switch, and a multilayered transient absorption network. This article studies transient heat transfer in the switch and provides a redefinition of the fuse curve as applied to the BSSCB suitable for digital control. This article identifies critical fault issues, discusses the impact on critical design points of the SuperCascode for a BSSCB, and provides design calculations for a complete 10-kV/300-A/3 X breaker, including the SuperCascode module. A scaled 6-kV/10-A/7 X SuperCascode is fabricated and tested to demonstrate switch response of <60 ns with fault isolation in 200 ns.}, number={4}, journal={IEEE Journal of Emerging and Selected Topics in Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Mehrotra, Utkarsh and Ballard, Bahji and Hopkins, Douglas C.}, year={2021}, pages={1–1} }
 @inproceedings{mehrotra_morgan_hopkins_2021, title={Design and Characterization of 3.3 kV-15 kV rated DBC Power Modules for Developmental Testing of WBG devices}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487311}, DOI={10.1109/APEC42165.2021.9487311}, abstractNote={An increasing number of power circuit designers are moving into designs at the bare die module-level to achieve greater circuit integration for lower inductance and better thermal management. Similarly, those who will use off-the-self modules are looking deeper inside the power modules to understand, discern, and optimize differences that impact gate driver design, power-loop designs and electro-physical layout between bare die. The ability for designers to have a greater understanding of the die-level module further advances adoption of WBG devices. This paper provides a description of open-source designs, fabrication, and test results for two DBC-based power modules. One is a SOT-227 footprint -based 6.5 kV DBC module, while the other is a 15 kV DBC module. The modules are specifically designed for mounting and testing new WBG power semiconductors under development, and as such, are designed for extreme operations under test. The characterization of the two modules and detailed insight into the ‘why’ in the design decisions provides the working engineer a clear understanding of variances in power module parameters and resulting effects on the module performance. The module designs are scalable, house single and multiple diodes and/or MOSFETs, include built-in current-sense and temperature monitoring, have Kelvin drain-source connections to reduce blanking-time, and utilize techniques to reduce stray inductance and resistance. The full designs are available for anyone’s use at www.go.ncsu.edu/prees_open_source}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Mehrotra, Utkarsh and Morgan, Adam J. and Hopkins, Douglas C.}, year={2021}, month={Jun}, pages={2351–2356} }
 @article{shah_narwal_bhattacharya_kanale_cheng_mehrotra_agarwal_baliga_hopkins_2021, title={Optimized AC/DC Dual Active Bridge Converter using Monolithic SiC Bidirectional FET (BiDFET) for Solar PV Applications}, ISSN={["2329-3721"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85123361428&partnerID=MN8TOARS}, DOI={10.1109/ECCE47101.2021.9595533}, abstractNote={Grid interface power conversion systems for commercial, industrial and residential solar power generation are becoming ubiquitous due to the competitive cost of solar energy. The AC/DC dual active bridge (DAB) converter is an upcoming topology in industrial PV energy and energy storage applications, providing bidirectional power transfer and galvanic isolation. In this paper, the properties of a DAB-type converter are leveraged to propose a design optimization process. It can optimize the high-frequency RMS current, size of magnetic elements and zero-voltage-switching (ZVS) region of the converter. The resulting design is compared against that derived from a conventional approach. In addition, an algorithm to compute the harmonic currents at the DC and line frequency AC ports of the system is proposed, and the respective filter designs are presented. The optimized design of the AC/DC DAB converter is implemented using the newly developed, 1200 V, $46 \mathrm{m}\Omega$, four quadrant, SiC-based monolithic bidirectional FETs (BiDFET). Experimental results from the 2.3 kW, $400\mathrm{V}/277\mathrm{V}_{{\mathrm {RMS}}}$ hardware prototype are finally presented to verify the design process.}, journal={2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Shah, Suyash Sushilkumar and Narwal, Ramandeep and Bhattacharya, Subhashish and Kanale, Ajit and Cheng, Tzu-Hsuan and Mehrotra, Utkarsh and Agarwal, Aditi and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2021}, pages={568–575} }