Works (2)
Updated: July 5th, 2023 15:35
2020 article
Slipstream Processors Revisited: Exploiting Branch Sets
2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), pp. 105–117.
author keywords: branch prediction; prefetching; hard-to-predict branch; delinquent load; pre-execution; helper threads; control independence
TL;DR:
The objective of this paper is to design a new pre-execution microarchitecture that meets four criteria: (i) retains the simpler coordination of a leader-follower microarch architecture, (ii) is fully automated with just hardware, (iii) targets both branches and loads, and is effective.
(via Semantic Scholar)
open access via www.lib.ncsu.edu (repository)
Source: Web Of Science
Added: March 8, 2021
2017 conference paper
H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor
2017 IEEE International Conference on Computer Design (ICCD), 145–152.
Event: 2017 IEEE International Conference on Computer Design (ICCD) at Boston, MA on November 5-8, 2017
TL;DR:
The H3 chip is presented, that uses 3D die stacking and novel microarchitecture to implement a heterogeneous multi-core processor (HMP) with low-latency fast thread migration capabilities and can reduce power consumption of benchmarks by up to 26%.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
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