Rhett Davis

Design Rule Checking with a CNN Based Feature Extractor

PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20).

Adaptive and reliable clock distribution design for 3-D integrated circuits

IEEE Transactions on Components Packaging and Manufacturing Technology, 4(11), 1862–1870.

Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC

2014 IEEE International Conference on IC Design & Technology (ICICDT).

Thermal pathfinding for 3-D ICs

IEEE Transactions on Components Packaging and Manufacturing Technology, 4(7), 1159–1168.

Design of controller for L2 cache mapped in Tezzaron stacked DRAM

2013 ieee international 3d systems integration conference (3dic).

Exploring early design tradeoffs in 3DIC

2013 ieee international symposium on circuits and systems (iscas), 545–549.

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

A transient electrothermal analysis of three-dimensional integrated circuits

IEEE Transactions on Components Packaging and Manufacturing Technology, 2(4), 660–667.

Area-efficient antenna-scalable MIMO detector for K-best sphere decoding

Journal of Signal Processing Systems for Signal Image and Video Technology, 68(2), 171–182.

Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels

IET Circuits, Devices & Systems, 6(1), 35.

Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(5), 676–689.

Leakage power contributor modeling

IEEE Design & Test of Computers, 29(2), 71–78.

Parallel transient simulation of multiphysics circuits using delay-based partitioning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(10), 1522–1535.

3D specific systems: Design and CAD

2011 20th asian test symposium (ats), 470–473.

Adaptive clock distribution for 3D integrated circuits

Ieee conference on electrical performance of electronic packaging and, 91–94.

Three-dimensional SRAM design with on-chip access time measurement

Electronics Letters, 47(8), 485–486.

Application exploration for 3-D integrated circuits: TCAM, FIFO, and FFT case studies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(4), 496–506.

Automated design space exploration for DSP applications

Journal of Signal Processing Systems for Signal Image and Video Technology, 56(2-3), 199–216.

Delay analysis and design exploration for 3D SRAM

2009 IEEE International Conference on 3d Systems Integration, 244–247.

Parallel merge algorithm for high-throughput signal processing applications

Electronics Letters, 45(3), 188–189.

The Benefits of 3D networks-on-chip as shown with LDPC decoding

2009 IEEE International Conference on 3d Systems Integration, 89–96.

H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor

Srinivasan, V., Chowdhury, R. B. R., Forbes, E., Widialaksono, R., Zhang, Z. Q., Schabel, J., … Franzon, P. D. 2017 ieee 35th international conference on computer design (iccd), 145–152.

Junction-level thermal extraction and simulation of 3DICs

Melamed, S., Thorolfsson, T., Srinivasan, A., Cheng, E., Franzon, P., & Davis, R. 2009 IEEE International Conference on 3d Systems Integration, 395–401.

Thermal raman and IR measurement of heterogeneous integration stacks

Harris, T. R., Pavlidis, G., Wyers, E. J., Newberry, D. M., Graham, S., Franzon, P., & Davis, W. R. Intersociety conference on thermal and thermomechanical phenomena in, 1505–1510.