Works (121)

Updated: April 4th, 2024 13:04

2021 article

A Virtual Platform for Object Detection Systems

2021 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC).

By: Q. Zhao n & W. Davis n

author keywords: Object Detection System; CNN; Hardware Accelerator; Power; Performance; Architecture; Virtual Platform
TL;DR: This paper will offer an virtual platform for object detection systems, and each component in the system will be simulated by a proper power model and a behavior model to help designers optimizeobject detection systems. (via Semantic Scholar)
UN Sustainable Development Goal Categories
Sources: Web Of Science, ORCID
Added: May 2, 2022

2021 article

An Instruction-Level Power and Energy Model for the Rocket Chip Generator

2021 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED).

By: Z. Wang n & W. Davis n

author keywords: Rocket chip; RISC-V; Energy characterization; Instruction-level; Power model
TL;DR: An event-based power modeling methodology is discussed which is the foundation of the model and is compatible with emerging power- and energy-modeling standards such as IEEE-2416, and validation results show that the proposed instruction-level power model achieves less than 3% error on simple C program benchmarks. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: November 1, 2021

2021 conference paper

Bridging the Organization Gap for EDA Machine Learning Data

Kalafala, K., Fu, H., Davis, W. R., Aadithya, K., & Clevenger, L. A. (2021, August 16). Presented at the DesignCon.

By: K. Kalafala, H. Fu, W. Davis, K. Aadithya & L. Clevenger

Event: DesignCon on August 16-28, 2021

Source: NC State University Libraries
Added: July 1, 2022

2021 article

Fast and Accurate PPA Modeling with Transfer Learning

2021 ACM/IEEE 3RD WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD).

By: L. Francisco n, P. Franzon n & W. Davis n

author keywords: PPA; Machine Learning; Power; Performance; Area; Gradient Boost; Neural Network; Transfer Learning
TL;DR: This work presents a machine learning approach using gradient boost models and neural networks to fast and accurately predict the power, performance, and area of a System-on-Chip (SoC) by reducing the number of samples used to create the models. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: November 15, 2021

2021 conference paper

Fast and Accurate PPA Modeling with Transfer Learning

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). Presented at the 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Munich, Germany.

By: W. Davis n, P. Franzon n, L. Francisco n, B. Huggins n & R. Jain*

Event: 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD) at Munich, Germany on November 1-4, 2021

author keywords: PPA; Machine Learning; Power; Performance; Area; Gradient Boost; Neural Network; Transfer Learning; Surrogate Modeling
TL;DR: The approach reached the same PPA solution as human designers in the same or fewer runs for a CORTEX-M0 system design, showing potential for automating the recipe optimization without needing more runs than a human designer would need. (via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure (OpenAlex)
Sources: Web Of Science, ORCID
Added: February 21, 2022

2021 speech

FreePDK3: A Novel PDK for Physical Verification at the 3nm Node

Sadangi, S., Pasumarthy, V., Pitts, W. S., & Davis, W. R. (2021, May). Presented at the Synopsys Speaker Series.

By: S. Sadangi, V. Pasumarthy, W. Pitts & W. Davis

Event: Synopsys Speaker Series on May 18, 2021

Source: NC State University Libraries
Added: July 1, 2022

2021 conference paper

System-Level Power Analysis with IEEE 2416 Power Models

Frenkil, J., Dhanwada, N., Davis, R., & Ratchkov, D. (2021, March 1). Workshop presented at the Design and Verification Conference and Exhibition (DVCON).

By: J. Frenkil, N. Dhanwada, R. Davis & D. Ratchkov

Event: Design and Verification Conference and Exhibition (DVCON) on March 1, 2021

Source: NC State University Libraries
Added: July 1, 2022

2021 conference paper

UPM/IEEE 2416 Power Modeling Standard: A Practitioner’s Perspective

Dhanwada, N., Davis, R., Dhanwada, N., & Frenkil, J. (2021, July 28). Embedded Tutorial presented at the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

By: N. Dhanwada, R. Davis, N. Dhanwada & J. Frenkil

Event: IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) on July 28, 2021

Source: NC State University Libraries
Added: July 1, 2022

2021 speech

Views from the Cloud

Davis, W. R. (2021, August). Panel Discussion presented at the Si2 Annual Technical Forum.

By: W. Davis

Event: Si2 Annual Technical Forum on August 6, 2021

Source: NC State University Libraries
Added: July 1, 2022

2020 speech

A Gentle Introduction to the Open Model Interface for Reliability Simulations

Davis, W. R. (2020, April). Presented at the Si2 OpenAccess Live Forum.

By: W. Davis

Event: Si2 OpenAccess Live Forum on April 24, 2020

Source: NC State University Libraries
Added: July 1, 2022

2020 speech

An Industry-standard approach toward modeling device aging

Davis, W. R., & Shaw, C. (2020, April). Virtual session video presented at the International Reliability Physics Symposium.

By: W. Davis & C. Shaw

Event: International Reliability Physics Symposium on April 28 - May 30, 2020

Source: NC State University Libraries
Added: July 1, 2022

2020 article

Design Rule Checking with a CNN Based Feature Extractor

PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20), pp. 9–14.

By: L. Francisco n, T. Lagare n, A. Jain n, S. Chaudhary n, M. Kulkarni n, D. Sardana n, W. Davis n, P. Franzon n

author keywords: Design Rule Checking; Machine Learning; IC Verification; Design for Manufacturing; Convolutional Neural Network; Deep Learning
TL;DR: The proof of feasibility for a fast interactive DRC engine that could be used during layout is established and the proposed model consists of a convolutional neural network trained to detect DRC violations. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: August 16, 2021

2020 conference paper

EDA Roadmap for Machine Learning & AI Standardization

Davis, W. R. (2020, January 30). EDA Roadmap for Machine Learning & AI Standardization. Panel Discussion, presented at the DesignCon, Santa Clara, CA.

By: W. Davis

Event: DesignCon at Santa Clara, CA on January 30, 2020

Source: NC State University Libraries
Added: July 1, 2022

2020 conference paper

How to write a compact reliability model with the Open Model Interface (OMI

2020 IEEE International Reliability Physics Symposium (IRPS). Presented at the 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX.

By: W. Davis n, C. Shaw & A. Hassan

Event: 2020 IEEE International Reliability Physics Symposium (IRPS) at Dallas, TX on April 28 - May 30, 2020

TL;DR: Semiconductor foundries became aware of this need, and one of them came up with an approach to modify model parameters through an interface to the simulator called the TMI, which was licensed to the Compact Model Coalition, which expanded and extended it, releasing it as Open Model Interface (OMI) to be used as a common platform for all foundries and model developers. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: July 1, 2022

2020 conference paper

System Level Power Analysis with UPM

Baker, A., Davis, W. R., Dhanwada, N., Frenkil, J., & Ratchkov, D. (2020, July 20). Virtual tutorial presented at the Design Automation Conference (DAC).

By: A. Baker, W. Davis, N. Dhanwada, J. Frenkil & D. Ratchkov

Event: Design Automation Conference (DAC) on July 20, 2020

Source: NC State University Libraries
Added: July 1, 2022

2019 journal article

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 66(2), 756–768.

By: J. Park n, W. Davis n & P. Franzon n

author keywords: Dynamic random access memory (DRAM); area and energy and timing model; circuit level model
TL;DR: 3-D-DATE is presented, a circuit-level dynamic random access memory (DRAM) area, timing, and energy model that models both the front and back end of 3-D integrated DRAM designs from 90–16 nm, across a broader range of emerging transistor devices and through-silicon vias. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: February 18, 2019

2019 conference paper

Characterization of Fast, Accurate Leakage Power Models for IEEE P2416

20th International Symposium on Quality Electronic Design (ISQED). Presented at the 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA.

By: B. Gupta n & W. Davis n

Event: 20th International Symposium on Quality Electronic Design (ISQED) at Santa Clara, CA on March 6-7, 2019

TL;DR: This paper presents the leakage power-model characterization approach in detail in the context of a simple four-gate circuit in order to bring accurate power-modeling capability to system-level digital design tools. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: July 1, 2022

2019 conference paper

Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes

Bhanushali, K., & Davis, W. R. (2019, March 14). Presented at the Free Silicon Conference (FSiC).

By: K. Bhanushali & W. Davis

Event: Free Silicon Conference (FSiC) on March 14-16, 2019

Source: NC State University Libraries
Added: July 1, 2022

2019 conference paper

Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools

20th International Symposium on Quality Electronic Design (ISQED). Presented at the 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA.

By: B. Huggins n, W. Davis n & P. Franzon n

Event: 20th International Symposium on Quality Electronic Design (ISQED) at Santa Clara, CA on March 6-7, 2019

TL;DR: This paper describes the use of estimated Pareto optimal trade-off sets to provide designers with the capability of visualizing the results of EDA tool configuration settings, or “knobs”, that will offer an optimal post detail route design based on two design metrics, critical path length and core area. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: July 1, 2022

2019 conference paper

Is Your AI-based EDA Tool Production-Ready?

Davis, W. R. (2019, June 3). Panel discussion presented at the Design Automation Conference.

By: W. Davis

Event: Design Automation Conference on June 3, 2019

Source: NC State University Libraries
Added: July 1, 2022

2019 speech

OpenAccess Partitions: How Fast Can We Go?

Davis, W. R. (2019, October). Presented at the Si2 OpenAccess Live Forum.

By: W. Davis

Event: Si2 OpenAccess Live Forum on October 18, 2019

Source: NC State University Libraries
Added: July 1, 2022

2019 conference paper

OpenAccess Partitions: How Fast Can We Go?

Davis, W. R. (2019, June 5). Presented at the Design Automation Conference, Las Vegas, NV.

By: W. Davis

Event: Design Automation Conference at Las Vegas, NV on June 5, 2019

Source: NC State University Libraries
Added: July 1, 2022

2019 conference paper

Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages

2019 International 3D Systems Integration Conference (3DIC). Presented at the 2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan.

By: T. Harris*, W. Davis n, S. Lipa n, W. Pitts n & P. Franzon n

Event: 2019 International 3D Systems Integration Conference (3DIC) at Sendai, Japan on October 8-10, 2019

TL;DR: This paper presents thermal measurement data of GaN HEMT on CMOS heterogeneous integration (HI) using a Diverse Accessible Heterogeneous Integration (DAHI) process and thermal T3ster measurements, a product and service available from Mentor are presented. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: July 1, 2022

2018 speech

Physical Design of a Stacked Heterogeneous Multi-Core Processor

Davis, W. R. (2018, January). Presented at the ARM Research, Cambridge, UK.

By: W. Davis

Event: ARM Research at Cambridge, UK on January 22, 2018

Source: NC State University Libraries
Added: July 1, 2022

2017 conference paper

H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor

2017 IEEE International Conference on Computer Design (ICCD), 145–152.

By: V. Srinivasan n, R. Chowdhury*, E. Forbes*, R. Widialaksono*, Z. Zhang*, J. Schabel n, S. Ku*, S. Lipa n ...

Event: 2017 IEEE International Conference on Computer Design (ICCD) at Boston, MA on November 5-8, 2017

TL;DR: The H3 chip is presented, that uses 3D die stacking and novel microarchitecture to implement a heterogeneous multi-core processor (HMP) with low-latency fast thread migration capabilities and can reduce power consumption of benchmarks by up to 26%. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2017 conference paper

Physical Design of a Stacked Heterogeneous Multi-Core Processor

Davis, W. R. (2017, September 19). Presented at the Oxford Circuits and Systems Conference, Oxford, UK.

By: W. Davis

Event: Oxford Circuits and Systems Conference at Oxford, UK on September 19, 2017

Source: NC State University Libraries
Added: July 1, 2022

2016 conference paper

Novel packaging and thermal measurement for 3D heterogeneous stacks

2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM). Presented at the 2016 International Symposium on 3D Power Electronics Integration and Manufacturing, Raleigh, NC.

By: T. Harris*, W. Davis* & P. Franzon*

Event: 2016 International Symposium on 3D Power Electronics Integration and Manufacturing at Raleigh, NC on June 13-15, 2016

Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2016 conference paper

Physical Design of a 3D-Stacked Heterogeneous Multi-Core Processor

2016 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2016 IEEE International 3D Systems Integration Conference (3DIC), -San Francisco, CA.

By: R. Widialaksono n, R. Chowdhury n, Z. Zhang n, J. Schabel n, S. Lipa n, E. Rotenberg n, W. Davis n, P. Franzon n

Event: 2016 IEEE International 3D Systems Integration Conference (3DIC) at -San Francisco, CA on November 8-11, 2016

TL;DR: This paper presents a 3D-SIC physical design methodology for a multi-core processor using commercial off-the-shelf tools and indicates an order of magnitude decrease in wirelengths for critical inter-core components in the 3D implementation compared to 2D implementations. (via Semantic Scholar)
Sources: NC State University Libraries, Crossref, ORCID
Added: March 24, 2019

2016 conference paper

Thermal raman and IR measurement of heterogeneous integration stacks

2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 1505–1510.

By: T. Harris n, G. Pavlidis*, E. Wyers*, D. Newberry n, S. Graham*, P. Franzon n, W. Davis n

Event: 2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) at Las Vegas, NV on May 31 - June 3, 2016

Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2015 conference paper

Computing in 3D

2015 International 3D Systems Integration Conference (3DIC). Presented at the 10.1109/3DIC.2015.7334571, Sendai, Japan.

By: P. Franzon n, E. Rotenberg n, W. Davis n, J. Tuck n, W. Davis, H. Zhou n, J. Schabel n, Z. Zhang n ...

Event: 10.1109/3DIC.2015.7334571 at Sendai, Japan on August 31 - September 2, 2015

TL;DR: The concept of Fast Thread Migration using 3DIC technologies is introduced and the design of a power optimized SIMD unit in which over half of the power is employed in the FP units is presented. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2015 chapter

FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology

In ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical Design (pp. 165–170).

By: K. Bhanushali n & W. Davis n

Event: 2015 Symposium on International Symposium on Physical Design at Monterey, CA

TL;DR: Design rules and layout guidelines for an open source predictive process design kit (PDK) for multi-gate 15nm FinFET devices and additional design rules are introduced considering process variability, and challenges involved in fabrication beyond 20nm. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: July 1, 2022

2015 journal article

Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks

2015 International 3D Systems Integration Conference (3DIC), 1–3.

By: T. Harris n, E. Wyers*, L. Wang*, S. Graham*, G. Pavlidis*, P. Franzon n, W. Davis n

Event: 2015 International 3D Systems Integration Conference (3DIC) at Sendai, Japan on August 31 - September 2, 2015

TL;DR: Preliminary results are presented which examine the thermal performance of the integration of materials such as GaN, InP, SiGe, and Si and two methods for building up the model of a test chip are compared. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2014 journal article

Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4(11), 1862–1870.

By: . Chen n, T. Zhu n, W. Davis n & P. Franzon n

author keywords: 3-D integrated circuit (3-D IC); adaptive; clock distribution; deskew; optimization; process-voltage-temperature (PVT) variation; stacking; thermal profile; through-silicon-via (TSV); tunable-delay-buffer (TDB)
TL;DR: A novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry is proposed and a thermal profile-based optimization flow is developed to further improve the power efficiency and reduce design overhead. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2014 chapter

Electrothermal Simulation of Three Dimensional Integrated Circuits

In R. Sharma (Ed.), Design of 3D Integrated Circuits and Systems. Boca Raton, FL: CRC Press.

By: S. Priyadarshi, J. Hu, M. Steer, P. Franzon & W. Davis

Ed(s): R. Sharma

Source: NC State University Libraries
Added: July 1, 2022

2014 conference paper

Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC

2014 IEEE International Conference on IC Design & Technology. Presented at the 2014 IEEE International Conference on IC Design & Technology (ICICDT).

By: S. Priyadarshi n, W. Davis n & P. Franzon n

Event: 2014 IEEE International Conference on IC Design & Technology (ICICDT)

TL;DR: A CAD flow and associated framework called Pathfinder3D is presented, which facilitates physically-aware system-level thermal simulation of 3DICs and facilitates early thermal evaluation of possible 3D design choices and thermal management techniques. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID, Crossref
Added: August 6, 2018

2014 journal article

Thermal Pathfinding for 3-D ICs

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4(7), 1159–1168.

By: S. Priyadarshi n, W. Davis n, M. Steer n & P. Franzon n

author keywords: 3-D IC; electronic system-level (ESL); electrothermal simulation; pathfinding; through-silicon via (TSV); transaction-level simulation
TL;DR: A pathfinding flow that integrates SystemC transaction-level electrical and dynamic thermal simulations to pass complex physical constraints to system architects in a convenient form is presented. (via Semantic Scholar)
UN Sustainable Development Goal Categories
Sources: Web Of Science, ORCID
Added: August 6, 2018

2014 conference paper

Towards a Standard Flow for System Level Power Modeling

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Presented at the 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA.

By: N. Dhanwada*, R. Davis n & J. Frenkil*

Event: 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) at San Jose, CA on November 2-6, 2014

TL;DR: This presentation will begin with an overview of existing gate level power modeling capabilities, using the Liberty modeling language as the example, and requirements beyond the existing gatelevel capabilities will be described. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2013 conference paper

Applications and design styles for 3DIC

2013 IEEE International Electron Devices Meeting. Presented at the 2013 IEEE International Electron Devices Meeting, Washington, DC.

By: P. Franzon n, E. Rotenberg n, J. Tuck n, W. Davis n, H. Zhou n, J. Schabel n, Z. Zhang n, J. Park n ...

Event: 2013 IEEE International Electron Devices Meeting at Washington, DC on December 9-11, 2013

TL;DR: 3D technologies offer significant potential to improve raw performance and performance per unit power and the next frontier is to create more sophisticated solutions that promise further increases in power/performance beyond those attributable to memory interfaces alone. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2013 conference paper

Design of controller for L2 cache mapped in Tezzaron stacked DRAM

2013 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA.

By: N. Tshibangu n, P. Franzon n, E. Rotenberg n & W. Davis n

Event: 2013 IEEE International 3D Systems Integration Conference (3DIC) at San Francisco, CA on October 2-4, 2013

TL;DR: This paper investigates the implementation of such a cache controller using 3-layer 256 MB Tezzaron Octopus stacked DRAM, which provides a fast data access through burst-4 and burst-8 mode and has a low hit latency. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2013 conference paper

Exploring early design tradeoffs in 3DIC

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 545–549.

By: P. Franzon n, S. Priyadarshi n, S. Lipa n, W. Davis n & T. Thorolfsson*

Event: 2013 IEEE International Symposium on Circuits and Systems (ISCAS) at Beijing, China on May 19-23, 2013

TL;DR: This paper explores some of the approaches to creating 3D specific designs and the CAD tools that can help in that exploration, together with early results from a thermal pathfinding tool. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2013 conference paper

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

By: S. Priyadarshi n, N. Choudhary n, B. Dwiel n, A. Upreti n, E. Rotenberg n, R. Davis n, P. Franzon n

Event: International Symposium on Quality Electronic Design (ISQED) at Santa Clara, CA on March 4-6, 2013

TL;DR: This work proposes exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP): 3D integration facilitates a technology alloy and application and microarchitectural heterogeneity is exploited to compensate for lower efficiency of old-technology cores. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2013 conference paper

Rationale for a 3D heterogeneous multi-core processor

2013 IEEE 31st International Conference on Computer Design (ICCD), 154–168.

By: E. Rotenberg n, B. Dwiel n, E. Forbes n, Z. Zhang n, R. Widialaksono n, R. Chowdhury n, N. Tshibangu n, S. Lipa n ...

Event: 2013 IEEE 31st International Conference on Computer Design (ICCD) at Asheville, NC on October 6-9, 2013

TL;DR: Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2012 journal article

A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2(4), 660–667.

By: T. Harris n, S. Priyadarshi n, S. Melamed n, C. Ortega*, R. Manohar*, S. Dooley*, N. Kriplani n, W. Davis n ...

author keywords: 3DIC; electrothermal effects; thermal management; transient analysis
UN Sustainable Development Goal Categories
Sources: Web Of Science, ORCID
Added: August 6, 2018

2012 journal article

Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 68(2), 171–182.

By: N. Moezzi-Madani n, T. Thorolfsson n, P. Chiang* & W. Davis n

author keywords: MIMO; K-best; Sphere decoder; VLSI
TL;DR: A reconfigurable in-place architecture that is scalable to an arbitrary number of antennas at run-time, while reducing area significantly compared with other sphere decoders, and to improve the throughput of the in-place architecture without any degradation in BER performance is proposed. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2012 journal article

Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels

IET Circuits, Devices & Systems, 6(1), 35.

By: S. Priyadarshi n, T. Harris n, S. Melamed n, C. Otero*, N. Kriplani n, C. Christoffersen*, R. Manohar*, S. Dooley* ...

TL;DR: The macromodel-based methodology enables robust and significantly faster dynamic electrothermal simulation over the long times required for thermal transients to subside and results in significant speed-up over transistor-level simulation for large-scale circuits. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Crossref, ORCID
Added: February 24, 2020

2012 journal article

Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(5), 676–689.

TL;DR: This paper presents a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect, and introduces a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity” in order to implement Power Blurring high definition (HD). (via Semantic Scholar)
UN Sustainable Development Goal Categories
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2012 journal article

Leakage Power Contributor Modeling

IEEE DESIGN & TEST OF COMPUTERS, 29(2), 71–78.

By: N. Dhanwada*, D. Hathaway*, J. Frenkil*, W. Davis n & H. Demircioglu n

TL;DR: An alternative “power contributor”based approach to cell leakage characterization that exploits inherent separability of power consumption for different portions of a cell is described. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2012 conference paper

Modeling Power Variability (from Small to Large

Davis, W. R. (2012, October 9). Presented at the Silicon Integration Inititative (Si2) Conference.

By: W. Davis

Event: Silicon Integration Inititative (Si2) Conference on October 9, 2012

Source: NC State University Libraries
Added: July 1, 2022

2012 journal article

Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 31(10), 1522–1535.

author keywords: Delay element; electrothermal simulation; multicore; multiphysics; parallel simulation; parallelization; transient simulation
TL;DR: A parallel delay-based iterative approach for interfacing delay-partitioned subcircuits is applied, which achieves the reasonable accuracy of nonparallel circuit simulation if both incorporate the same interblock delay. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2012 journal article

Pathfinder 3D: A Flow for System-Level Design Space Exploration

2011 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan.

By: S. Priyadarshi n, J. Hu n, W. Choi n, S. Melamed n, X. Chen n, W. Davis n, P. Franzon n

Event: 2011 IEEE International 3D Systems Integration Conference (3DIC) at Osaka, Japan on January 31 - February 2, 2011

TL;DR: A flow for fast system-level exploration useful for path finding studies and a free open source design kit compiler, FreePDK3D45, and a tool for fast floorplan evaluation of TSV-based digital architectures, Pathfinder3D. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2011 conference paper

3D specific systems: Design and CAD

2011 Asian Test Symposium, 470–473.

By: P. Franzon n, W. Davis n, T. Thorolfsson n & S. Melamed n

Event: 2011 Asian Test Symposium at New Delhi, India on November 20-23, 2011

author keywords: 3DIC; 3D IC; three dimensional IC; TSV; stacked memory; memory on logic; FFT
UN Sustainable Development Goal Categories
Sources: Web Of Science, ORCID
Added: August 6, 2018

2011 conference paper

Adaptive clock distribution for 3D integrated circuits

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 91–94.

By: X. Chen n, W. Davis n & P. Franzon n

Event: 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems at San Jose, CA on October 23-26, 2011

TL;DR: A robust tunable-delay-buffer circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry in 3D ICs. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2011 conference paper

An energy-efficient 64-QAM MIMO detector for emerging wireless standards

2011 Design, Automation & Test in Europe. Presented at the 2011 Design, Automation & Test in Europe, Grenoble, France.

By: N. Moezzi-Madani n, T. Thorolfsson n, J. Crop*, P. Chiang* & W. Davis n

Event: 2011 Design, Automation & Test in Europe at Grenoble, France on March 14-18, 2011

TL;DR: A new architecture for the K-best detector is proposed, which unlike the popular multi-stage architecture used for K- best detectors, implements just one core and reduces the total power consumption by 27%, without any noticeable performance degradation. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2011 speech

Architecture, Design, and CAD for 3D-ICs

Davis, W. R. (2011, October). Presented at the Institute of Microelectronics, Agency for Science, Technology, and Research (A*STAR), Singapore.

By: W. Davis

Event: Institute of Microelectronics, Agency for Science, Technology, and Research (A*STAR) at Singapore on October 3, 2011

Source: NC State University Libraries
Added: July 1, 2022

2011 journal article

Coordinating 3D designs: Interface IP, standards or free form?

2011 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan.

By: P. Franzon n, W. Davis n, Z. Zhou n, S. Priyadarshi n, M. Hogan*, T. Karnik*, G. Srinivas

Event: 2011 IEEE International 3D Systems Integration Conference (3DIC) at Osaka, Japan on January 31 - February 2, 2011

TL;DR: This paper proposes that 3D chip stack management should be managed through an Interface IP approach Design blocks with associated properties that not only supports signaling and power delivery but also constraints that must be managed between chips both during design but also in-situ and as part of physical verification. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2011 chapter

Design and Computer Aided Design of 3DIC

In A. Sheibanyrad, F. Pétrot, & A. Jantsch (Eds.), 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems (pp. 75–88).

By: P. Franzon n, W. Davis & T. Thorolfsson

Ed(s): A. Sheibanyrad, F. Pétrot & A. Jantsch

TL;DR: This chapter reviews the process of 3DIC designing exploiting Through Silicon Via (TSV) technology and introduces the notion of re-architecting systems explicitly to exploit high density TSV processes. (via Semantic Scholar)
UN Sustainable Development Goal Categories
Sources: Web Of Science, ORCID
Added: July 9, 2022

2011 chapter

Predictive Process Design Kits

In Y. Cao (Ed.), Predictive Technology Model for Robust Nanoelectronic Design. Integrated Circuits and Systems (pp. 121–140).

By: W. Davis n & H. Demircioglu n

Ed(s): Y. Cao

TL;DR: For nearly half a century, semiconductor technology has continued to deliver exponential growth in the number of transistors on a chip, but the cracks are showing in the industry’s armor. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2011 conference paper

Test & Reliability Challenges in 3D NoCs

Davis, W. R. (2011, June 5). Test & Reliability Challenges in 3D NoCs. Presented at the Design Automation Conference (DAC) Workshop on Diagnostic Services in Networks-on-Chip: Test, Debug, & On-Line Monitoring.

By: W. Davis

Event: Design Automation Conference (DAC) Workshop on Diagnostic Services in Networks-on-Chip: Test, Debug, & On-Line Monitoring on June 5, 2011

Source: NC State University Libraries
Added: July 1, 2022

2011 journal article

Three-dimensional SRAM design with on-chip access time measurement

ELECTRONICS LETTERS, 47(8), 485–486.

By: X. Chen n, T. Zhu n & W. Davis n

UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2010 conference paper

A Low-Area Flexible MIMO Detector for WiFi/WiMAX Standards

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). Presented at the 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, Germany.

By: N. Moezzi-Madani n, T. Thorolfsson n & W. Davis n

Event: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) at Dresden, Germany on March 8-12, 2010

TL;DR: A very low area reconfigurable MIMO detector which achieves a high throughput of 103Mbps and uses 27 Kilo Gates when implemented in a commercial 180nm CMOS process. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2010 conference paper

Algorithm and hardware complexity reduction techniques for k-best sphere decoders

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI, 471–476.

By: N. Moezzi-Madani n, T. Thorolfsson n & W. Davis n

Event: Great Lakes Symposium on VLSI (GLSVLSI

TL;DR: This work introduces three techniques to reduce the power consumption of MIMO detectors and increase their data rate, and decreases the complexity of the K-best sphere decoder effectively by using the MMSE-SQRD channel processing technique. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2010 conference paper

Creating 3D Specific Systems: Architecture, Design and CAD

International Symposium on Microelectronics, 2010(1), 23–27.

By: P. Franzon n, W. Davis n, T. Thorolfsson n & S. Melamed n

Event: Intlernational Microelectronics and Packaging Society (iMAPS) Symposium at Raleigh, NC

TL;DR: This abstract explores application drivers, design and CAD for 3D ICs, and critical areas that need better solutions are explored, including design planning, test management, and thermal management. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2010 conference paper

Creating 3D Specific Systems: Architecture, Design, and CAD

2010 Design, Automation & Test in Europe Conference & Exhibition, 1684–1688.

By: P. Franzon n, W. Davis n & T. Thorolfsson

Event: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) at Dresden, Germany on March 8-12, 2010

Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2010 conference paper

Investigation of tier-swapping to improve the thermal profile of memory-on-logic 3DICs

Melamed, S., Thorolfsson, T., Srinivasan, A., Cheng, E., Franzon, P., & Davis, W. R. (2010, October). Presented at the International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).

By: S. Melamed, T. Thorolfsson, A. Srinivasan, E. Cheng, P. Franzon & W. Davis

Event: International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) on October 6-8, 2010

Source: NC State University Libraries
Added: July 1, 2022

2010 journal article

Low Power Hypercube Divided Memory FFT Engine Using 3D Integration

ACM Transactions on Design Automation of Electronic Systems, 16(1), 1–25.

By: T. Thorolfsson n, S. Melamed n, W. Davis n & P. Franzon n

author keywords: Design; 3DIC; scaling; TSV; FFT
TL;DR: A floating point FFT processor is demonstrated that leverages both 3D integration and a unique hypercube memory division scheme to reduce the power consumption of a 1024 point F FT down to 4.227μJ. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2010 conference paper

Modeling Layout-Dependent Stress Effects: Opportunities for OpenDFM

Davis, W. R. (2010, June 13). Presented at the Design Automation Conference (DAC) Open Design-for-Manufacturability (OpenDFM) Workshop.

By: W. Davis

Event: Design Automation Conference (DAC) Open Design-for-Manufacturability (OpenDFM) Workshop on June 13, 2010

Source: NC State University Libraries
Added: July 1, 2022

2010 conference paper

Thermal Adaptive Clock Design for 3D Integrated Circuits

Chen, X., & Davis, W. R. (2010, September 13). Presented at the Semiconductor Research Corporation (SRC) TECHCON.

By: X. Chen & W. Davis

Event: Semiconductor Research Corporation (SRC) TECHCON on September 13-14, 2010

Source: NC State University Libraries
Added: July 1, 2022

2010 conference paper

Thermal analysis and verification of a mounted monolithic integrated circuit

Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon), 37–40.

By: T. Harris n, S. Melamed n, S. Luniya n, W. Davis n, M. Steer n, L. Doxsee*, K. Obermiller n, C. Hawkinson n

Event: IEEE SoutheastCon 2010 (SoutheastCon) at Concord, NC on March 18-21, 2010

author keywords: MMIC; electrothermal; heat transfer; simulators; compact modeling; fREEDA
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (Web of Science; OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2009 journal article

Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 17(4), 496–506.

By: W. Davis n, E. Oh n, A. Sule n & P. Franzon n

author keywords: Fast Fourier transform (FFT); first-in first-out (FIFO); ternary content-addressable memory (TCAM); 3-D integrated circuit (IC)
TL;DR: This paper presents physical-design case studies of ternary content-addressable memories, first-in first-out (FIFO) memories, and a 8192-point fast Fourier transform (FFT) processor in order to quantify the benefit of the through-silicon vias in an available 180-nm 3-D process. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2009 journal article

Automated Design Space Exploration for DSP Applications

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 56(2-3), 199–216.

By: R. Hourani n, R. Jenkal n, W. Davis n & W. Alexander n

author keywords: Hardware design; VLSI; Synthesis; RTL; Area; Throughput; Power dissipation; DSP; FIR filter
TL;DR: This work aims at performing hardware optimizations at the architectural and arithmetic levels, relieving the user from manually describing the designs at the register transfer level and iteratively varying the hardware structures. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2009 conference paper

Delay analysis and design exploration for 3D SRAM

2009 IEEE International Conference on 3d Systems Integration, 244–247.

By: X. Chen n & W. Davis n

TL;DR: This paper presents a physical based delay analysis approach to explore 3D SRAM design options and shows that the optimized 3D sub-array provides up to 20% extra improvement for SRAM access time reduction. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2009 conference paper

High-Throughput Low-Complexity MIMO Detector Based on K-Best Algorithm

GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI, 451–456.

By: N. Moezzi-Madani & W. Davis

Event: Great Lakes Symposium on VLSI (GLSVLSI on May 10-12, 2009

Source: NC State University Libraries
Added: July 9, 2022

2009 conference paper

Junction-level thermal extraction and simulation of 3DICs

2009 IEEE International Conference on 3d Systems Integration, 395–401.

By: S. Melamed n, T. Thorolfsson n, A. Srinivasan*, E. Cheng*, P. Franzon n & R. Davis n

Event: 2009 IEEE International Conference on 3D System Integration at San Francisco, CA on September 28-30, 2009

TL;DR: It was found that lowering the simulation resolution and using composite thermal conductivities failed to accurately predict the location of these tentpoles, so large isolated temperature spikes were found near groups of clock buffers at the edge of the SRAMs on the middle tier. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2009 journal article

Parallel merge algorithm for high-throughput signal processing applications

ELECTRONICS LETTERS, 45(3), 188–189.

By: N. Moezzi-Madani n & W. Davis n

TL;DR: A parallel merge algorithm is proposed that results in a smaller critical-path delay than all of the other merge algorithms explored, which effectively increases the throughput of VLSI signal processing systems. (via Semantic Scholar)
UN Sustainable Development Goal Categories
Sources: Web Of Science, ORCID
Added: August 6, 2018

2009 speech

Prototyping in 3D-ICs: Design Flow Needs

Davis, W. R. (2009, October). Presented at the Silicon Integration Inititative (Si2) and Global Semiconductor Association (GSA) Workshop on Requirements for 3D Design Flow Interoperability Standards.

By: W. Davis

Event: Silicon Integration Inititative (Si2) and Global Semiconductor Association (GSA) Workshop on Requirements for 3D Design Flow Interoperability Standards on October 1, 2009

Source: NC State University Libraries
Added: July 1, 2022

2009 speech

Save Your Energy: A Fast and Accurate Approach to NoC Power Estimation

Mineo, C., & Davis, W. R. (2009, February). Presented at the Workshop on 3D Integration and Interconnect-Centric Architectures (in conjunction with the International Symposium on High Performance Computer Architecture.

By: C. Mineo & W. Davis

Event: Workshop on 3D Integration and Interconnect-Centric Architectures (in conjunction with the International Symposium on High Performance Computer Architecture on February 15, 2009

Source: NC State University Libraries
Added: July 1, 2022

2009 speech

The Benefits of 3D Networks-on-Chip

Davis, W. R. (2009, December). Presented at the Silicon Integration Initiative (Si2) Low-Power Coalition Technical Steering Group Web-Meeting.

By: W. Davis

Event: Silicon Integration Initiative (Si2) Low-Power Coalition Technical Steering Group Web-Meeting on December 10, 2009

Source: NC State University Libraries
Added: July 1, 2022

2009 conference paper

The Benefits of 3D networks-on-chip as shown with LDPC decoding

2009 IEEE International Conference on 3d Systems Integration, 89–96.

By: C. Mineo n & W. Davis n

TL;DR: The core is a fast, high level transaction-based NoC simulator, which accesses carefully compiled power, timing, and area models for basic NoC componets built from detailed circuit simulation. (via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2008 conference paper

An 8192-point Fast Fourier Transform 3D-IC Case Study

2008 51st Midwest Symposium on Circuits and Systems, 438–441.

By: W. Davis n, A. Sule* & P. Franzon n

Event: 2008 51st Midwest Symposium on Circuits and Systems at Knoxville, TN on August 10-13, 2008

TL;DR: This paper presents a case studies of an 8192-point fast Fourier transform (FFT) processor in order to quantify the benefit of the through-silicon vias in an available 180 nm 3D process. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID, Crossref
Added: March 24, 2019

2008 speech

An Architecture Evaluator for Three-Dimensional Integrated Circuits

Davis, W. R. (2008, May). Presented at the Stanford University ECE Department Seminar.

By: W. Davis

Event: Stanford University ECE Department Seminar on May 22, 2008

Source: NC State University Libraries
Added: July 1, 2022

2008 conference paper

An Efficient VLSI Implementation for the 1D Convolutional Discreet Wavelet Transform

2008 51st Midwest Symposium on Circuits and Systems. Presented at the 2008 51st Midwest Symposium on Circuits and Systems, Knoxville, TN.

By: R. Hourani n, I. Dalal n, W. Davis n, C. Doss* & W. Alexander n

Event: 2008 51st Midwest Symposium on Circuits and Systems at Knoxville, TN on August 10-13, 2008

TL;DR: The proposed architecture combines several optimizations that improve the performance of the hardware design in terms of throughput and power dissipation and an analytical comparison with other existing DWT implementations illustrates a two fold improvement in throughput. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2008 speech

Automation and Back-End Design within the FreePDK OpenAccess 45nm PDK and Cell Libraries for University Flows

Davis, W. R. (2008, June). Presented at the Semiconductor Research Corporation (SRC) e-Workshop.

By: W. Davis

Event: Semiconductor Research Corporation (SRC) e-Workshop on June 26, 2008

Source: NC State University Libraries
Added: July 1, 2022

2008 conference paper

Computer-Aided Design and Application Exploration for 3D Integrated Circuits

Proceedings of the Government Microcircuit Applications & Critical Technology (GOMACTech) Conference. Presented at the Government Microcircuit Applications & Critical Technology (GOMACTech) Conference.

By: P. Franzon, W. Davis, M. Steer, H. Hua, S. Lipa, S. Luniya, C. Mineo, J. Oh ...

Event: Government Microcircuit Applications & Critical Technology (GOMACTech) Conference on March 17-20, 2008

Source: NC State University Libraries
Added: July 1, 2022

2008 conference paper

Design and CAD for 3D Integrated Circuits

DAC '08: Proceedings of the 45th annual Design Automation Conference, 668–673.

By: P. Franzon n, W. Davis n, M. Steer n, S. Lipa n, E. Oh n, T. Thorolfsson n, S. Melamed n, S. Luniya n ...

Event: Design Automation Conference (DAC)

TL;DR: This paper presents several case studies that are uniquely enhanced through 3D implementation, including a 3D CAM, an FFT processor, and a SAR processor, which requires higher fidelity thermal modeling than 2DIC design. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2008 speech

FreePDK: A Free OpenAccess 45nm PDK and Cell Library for Universities

Davis, W. R. (2008, October). Presented at the Semiconductor Research Corporation (SRC) e-Workshop.

By: W. Davis

Event: Semiconductor Research Corporation (SRC) e-Workshop on October 3, 2008

Source: NC State University Libraries
Added: July 1, 2022

2008 conference paper

Inter-Die Signaling in Three Dimensional Integrated Circuits

2008 IEEE Custom Integrated Circuits Conference. Presented at the 008 IEEE Custom Integrated Circuits Conference, San Jose, CA.

By: C. Mineo n, R. Jenkal n, S. Melamed n & W. Davis n

Event: 008 IEEE Custom Integrated Circuits Conference at San Jose, CA on September 21-24, 2008

TL;DR: This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18 mum MIT Lincoln Laboratories 3D FDSOI 1.5 V process, and establishes the need for a 3D network simulator to quantify the advantage 3D circuit implementations have over 2D. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2007 journal article

3D Interconnect Device Design: Theory vs. Reality

Future Fab International, (23), 38–40.

By: W. Davis, A. Sule & K. Schoenfliess

Source: NC State University Libraries
Added: July 1, 2022

2007 speech

3D-IC Design: Theory vs. Reality

Davis, W. R. (2007, June). Presented at the University of Utah ECE Department Seminar, Salt Lake City, UT.

By: W. Davis

Event: University of Utah ECE Department Seminar at Salt Lake City, UT on June 21, 2007

Source: NC State University Libraries
Added: July 1, 2022

2007 conference paper

An Architecture for Energy Efficient Sphere Decoding

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design, 244–249.

By: R. Jenkal n & W. Davis n

Event: International Symposium on Low Power Electronics and Design (ISLPED on August 27-29, 2007

TL;DR: This work proposes an improved architecture that aims to exploit a combination of a deeper pipeline and the use of single-port read and write memories to increase the energy efficiency ofSphere decoding. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2007 conference paper

Design for 3D Integration and Applications

2007 International Symposium on Signals, Systems and Electronics, 263–266,

By: P. Franzon n, W. Davis n, M. Steer n, H. Hao n, S. Lipa n, S. Luniya n, C. Mineo n, J. Oh n ...

Event: 2007 International Symposium on Signals, Systems and Electronics at Montreal, Quebec, Canada on July 30 - August 2, 2007

TL;DR: This paper explores application drivers and computer aided design (CAD) for 3D ICs in order to provide system advantages equivalent to up to two technology nodes of scaling. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID, Crossref
Added: March 24, 2019

2007 conference paper

Designing FIFO Buffers using 3DIC Technology

VLSI Multilevel Interconnection (VMIC) Conference, 267–272.

By: A. Sule & W. Davis

Event: VLSI Multilevel Interconnection (VMIC) Conference on September 25-28, 2007

Source: NC State University Libraries
Added: July 1, 2022

2007 speech

Energy-Efficient Sphere Decoding (and other research efforts

Davis, W. R. (2007, September). Presented at the DARPA/OSD Trusted Foundry Circuit Designers Meeting, Essex Junction, VT.

By: W. Davis

Event: DARPA/OSD Trusted Foundry Circuit Designers Meeting at Essex Junction, VT on September 13, 2007

Source: NC State University Libraries
Added: July 1, 2022

2007 conference paper

FreePDK: An Open Source, OpenAccess Design Kit

Davis, W. R. (2007, November 5). Presented at the OpenAccess Conference.

By: W. Davis

Event: OpenAccess Conference on November 5, 2007

Source: NC State University Libraries
Added: July 1, 2022

2007 conference paper

FreePDK: An Open-Source Variation-Aware Design Kit

2007 IEEE International Conference on Microelectronic Systems Education (MSE'07). Presented at the 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), San Diego, CA.

By: J. Stine*, I. Castellanos*, M. Wood*, J. Henson*, F. Love*, W. Davis n, P. Franzon n, M. Bucher n ...

Event: 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07) at San Diego, CA on June 3-4, 2007

TL;DR: An open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45 nm, for use in VLSI research, education and small businesses is discussed. (via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure (OpenAlex)
Sources: Web Of Science, ORCID, Crossref
Added: March 24, 2019

2006 conference paper

Architecture for Energy Efficient Sphere Decoding

2006 IEEE International SOC Conference, 267–270.

By: R. Jenkal n, H. Hua n, A. Sule n & W. Davis n

Event: 2006 IEEE International SOC Conference at Austin, TX on September 24-27, 2006

TL;DR: An improved architecture forSphere Decoding is provided which aims to increase overall energy efficiency (b/s/mW) of the decoder and is based on a novel implementation which combines the use of a deeply pipelined data-path and "multi symbol vector" based approach to exploit the pipeline. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2006 chapter

Automated Architectural Exploration for Signal Processing Algorithms

In 2006 IEEE Workshop on Signal Processing Systems Design and Implementation (pp. 274–279,).

By: R. Hourani n, R. Jenkal n, W. Davis n & W. Alexander n

Event: 2006 IEEE Workshop on Signal Processing Systems Design and Implementation at Banff, AB, Canada on October 2-4, 2006

TL;DR: This paper presents the view of a framework that combines common electronic design automation (EDA) tools to alleviate the designer from manually constructing the hardware models and analyzing their performance, and uses this framework to efficiently implement design optimizations that improve the performance of the overall hardware architectures. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2006 conference paper

Breaking Rent’s Rule: Opportunities for 3D Interconnect Networks

VLSI Multilevel Interconnection (VMIC) Conference, 228–233.

By: W. Davis & C. Mineo

Event: VLSI Multilevel Interconnection (VMIC) Conference on September 26-28, 2006

Source: NC State University Libraries
Added: July 1, 2022

2006 conference paper

Compact Electrothermal Modeling of an X-band MMIC

2006 IEEE MTT-S International Microwave Symposium Digest, 651–654.

By: S. Luniya n, W. Batty*, V. Caccamesi, M. Garcia, C. Christoffersen*, S. Melamed n, W. Davis n, M. Steer n

Event: 2006 IEEE MTT-S International Microwave Symposium at San Francisco, CA on June 11-16, 2006

author keywords: MMIC; electrothermal effects; circuit simulation; modeling
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (Web of Science; OpenAlex)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2006 speech

Demystifying 3D ICs: The Pros and Cons of Going Vertical

Davis, W. R. (2006, April). Presented at the Virginia Tech ECE Department Seminar, Blacksburg, VA.

By: W. Davis

Event: Virginia Tech ECE Department Seminar at Blacksburg, VA on April 14, 2006

Source: NC State University Libraries
Added: July 1, 2022

2006 conference paper

Exploring Compromises among Timing, Power and Temperature in Three-Dimensional Integrated Circuits

DAC '06: Proceedings of the 43rd annual Design Automation Conference, 997–1002.

By: H. Hua n, C. Mineo n, K. Schoenfliess n, A. Sule n, S. Melamed n, R. Jenkal n, W. Davis n

Event: Design Automation Conference (DAC)

TL;DR: Physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology, and it is shown that thermal-vias offer no performance benefit for the low- power system and only marginal benefit forThe high- performance system. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2006 conference paper

Performance Trend in Three-Dimensional Integrated Circuits

2006 International Interconnect Technology Conference, 45–47.

By: H. Hua n, C. Mineo n, K. Schoenfliess n, A. Sule n, S. Melamed n & W. Davis n

Event: 2006 International Interconnect Technology Conference at Burlingame, CA on June 5-7, 2006

TL;DR: This work develops an automated design flow with 2D CAD tools to design 3DICs with the MIT Lincoln Lab 0.18mum three-tier fully depleted silicon on insulator (FDSOI) process, showing that the performance of3DIC shows up to two-generation advantage over its 2D counterpart with only three tiers. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2006 speech

Tool Integration for Signal Processing Architectural Exploration

Hourani, R., Jenkal, R., Davis, R., & Alexander, W. (2006, April). Presented at the Electronic Design Process (EDP) Workshop.

By: R. Hourani, R. Jenkal, R. Davis & W. Alexander

Event: Electronic Design Process (EDP) Workshop

Source: NC State University Libraries
Added: July 1, 2022

2005 journal article

Demystifying 3D ICs: The procs and cons of going vertical

IEEE DESIGN & TEST OF COMPUTERS, 22(6), 498–510.

By: W. Davis n, J. Wilson n, S. Mick n, M. Xu*, H. Hua*, C. Mineo n, A. Sule n, M. Steer n, P. Franzon n

TL;DR: A practical introduction to the design trade-offs of the currently available 3D IC technology options is provided, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. (via Semantic Scholar)
UN Sustainable Development Goal Categories
Sources: Web Of Science, ORCID
Added: August 6, 2018

2005 conference paper

OpenAccess Tools for 3D Integration

Davis, W. R. (2005, November 10). Presented at the OpenAccess Conference, San Jose, CA.

By: W. Davis

Event: OpenAccess Conference at San Jose, CA on November 10, 2005

Source: NC State University Libraries
Added: July 1, 2022

2005 conference paper

Pre-route Net Classing for Crosstalk Avoidance

Hua, H., Sule, A., Mineo, C., & Davis, W. R. (2005, September 12). Presented at the Cadence Designer Network Live Conference (CDNLive), San Jose, CA.

By: H. Hua, A. Sule, C. Mineo & W. Davis

Event: Cadence Designer Network Live Conference (CDNLive) at San Jose, CA on September 12-13, 2005

Source: NC State University Libraries
Added: July 1, 2022

2005 conference paper

Wire-Delay Reduction Analysis of a 3-Tier, 8-Point Fast Fourier Transform 3D-IC

VLSI Multilevel Interconnection (VMIC) Conference, 474–479.

By: W. Davis, H. Hua, A. Sule, C. Mineo, S. Melamed, M. Steer, P. Franzon

Event: VLSI Multilevel Interconnection (VMIC) Conference

Source: NC State University Libraries
Added: July 1, 2022

2004 conference paper

Multi-Parameter Power Minimization of Synthesized Datapaths

IEEE Computer Society Annual Symposium on VLSI, 151–157.

By: W. Davis n, A. Sule n & H. Hua n

Event: IEEE Computer Society Annual Symposium on VLSI at Lafayette, LA on February 19-20, 2004

TL;DR: The possibility of using convex optimization to solve the multi-parameter optimization problem is explored and a case-study of an 8-bit multiply-accumulate block, which is optimized in 250nm and 70nm technologies is presented. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2003 journal article

500 Mb/s Soft Output Viterbi Decoder

IEEE Journal of Solid State Circuits, 38(7), 1234–1241.

By: E. Yeo*, S. Augsburger*, W. Davis n & B. Nikolić*

author keywords: iterative decoders; turbo codes; Viterbi decoder; VLSI
TL;DR: Two 8-state, 7-bit soft output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in 0.18µm CMOS technology, which has been demonstrated to achieve information rates very close to the Shannon limit. (via Semantic Scholar)
Source: Web Of Science
Added: July 9, 2022

2003 conference paper

Automated Design Flows for High-Performance Systems

Davis, W. R. (2003, February 11). Presented at the OpenAccess Conference, San Jose, CA.

By: W. Davis

Event: OpenAccess Conference at San Jose, CA on February 11, 2003

Source: NC State University Libraries
Added: July 1, 2022

2003 conference paper

Getting High-Performance Silicon from System-Level Design

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 238–243.

By: W. Davis n

Event: IEEE Computer Society Annual Symposium on VLSI at Tampa, FL on February 20-21, 2003

TL;DR: This paper presents a brief summary of Platform-based design, SystemC, and Chip-in-a-day, in order to propose that more system-level abstraction of physical performance is needed to make these techniques more useful. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2003 chapter

Real-Time System-on-a-Chip Emulation

In G. Martin & H. Chang (Eds.), Winning the SoC Revolution (pp. 229–253).

By: K. Kuusilinna*, C. Chang*, H. Bluethgen*, W. Davis n, B. Richards*, B. Nikolić*, R. Brodersen*

Ed(s): G. Martin* & H. Chang*

TL;DR: A comprehensive design flow for digital systems from high-level algorithmic specifications to FPGA-based emulation and final ASIC implementation is presented, enabling rapid system development and easing the verification burden. (via Semantic Scholar)
Sources: NC State University Libraries, ORCID
Added: July 9, 2022

2003 speech

System-Level Design: Past, Present, and Future

Davis, W. R. (2003, February). Presented at the University of Tennessee ECE Department Seminar, Knoxville, TN.

By: W. Davis

Event: University of Tennessee ECE Department Seminar at Knoxville, TN

Source: NC State University Libraries
Added: July 1, 2022

2002 conference paper

500 Mb/s Soft Output Viterbi Decoder

European Solid-State Circuits Conference (ESSCIRC), 523–526,

By: E. Yeo, S. Augsburger, W. Davis & B. Nikolić

Event: European Solid-State Circuits Conference (ESSCIRC)

Source: NC State University Libraries
Added: July 1, 2022

2002 journal article

A Design Environment for High-Throughput, Low-Power Dedicated Signal Processing Systems

IEEE Journal of Solid State Circuits, 37(3), 420–431.

By: W. Davis*, N. Zhang, K. Camera*, D. Marković*, T. Smilkstein*, M. Ammer*, E. Yeo*, S. Augsburger*, B. Nikolić*, R. Brodersen*

author keywords: application specific integrated circuits; design automation; design methodology; integrated circuit design; parallel architectures; system analysis and design
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2002 thesis

A Hierarchical, Automated Design Flow for Low-Power, High-Throughput Digital Signal Processing IC’s

(PhD Thesis). Electrical Engineering Department, University of California, Berkeley.

By: W. Davis

Source: NC State University Libraries
Added: July 1, 2022

2002 conference paper

Implementation of high throughput soft output viterbi decoders

IEEE Workshop on Signal Processing Systems, 146–151.

By: E. Yeo*, S. Augsburger*, W. Davis* & B. Nikolić*

Event: IEEE Workshop on Signal Processing Systems at San Diego, CA on October 16-18, 2002

TL;DR: The architectural considerations for VLSI implementations of soft output Viterbi decoders are presented, and structural transformation of the add-compare-select structures provides high throughput with small area overhead. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2001 conference paper

A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 545–548.

By: W. Davis*, N. Zhang*, K. Camera*, F. Chen*, D. Marković*, N. Chan*, B. Nikolic*, R. Brodersen*

Event: IEEE 2001 Custom Integrated Circuits Conference at San Diego, CA on May 9, 2001

TL;DR: A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented, and automatic characterization of layout improves system-level estimates. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: July 9, 2022

2001 conference paper

An Automated Design Flow for Low-Power, High-Throughput Dedicated Signal Processing Systems

Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, 475–480.

By: W. Davis*, N. Zhang*, K. Camera*, D. Marković*, T. Smilkstein*, N. Chan*, M. Ammer*, E. Yeo*, B. Nikolić*, R. Brodersen*

Event: Thirty-Fifth Asilomar Conference on Signals, Systems and Computers at Pacific Grove, CA on November 4-7, 2001

TL;DR: A system-level perspective of a hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits and a detailed example of the design process for a DS SS TDMA baseband receiver are presented. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: July 9, 2022

2001 speech

An Automated Design Flow for Low-Power, High-Throughput Dedicated Signal Processing Systems

Davis, W. R. (2001, December). Presented at the MathWorks, Inc. seminar Innovation First: System Level Design for DSP and Communications, Waltham, MA.

By: W. Davis

Event: MathWorks, Inc. seminar Innovation First: System Level Design for DSP and Communications at Waltham, MA on December 4, 2001

Source: NC State University Libraries
Added: July 1, 2022

2001 speech

Design Technology for Low Power Radio Systems

Davis, W. R. (2001, September). Presented at the Computer Aided Network Design Workshop (CANDE), Grand Teton, WY.

By: W. Davis

Event: Computer Aided Network Design Workshop (CANDE) at Grand Teton, WY on September 20-22, 2001

Source: NC State University Libraries
Added: July 1, 2022

2001 conference paper

Wireless systems-on-a-chip design

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers, 45–48.

By: R. Brodersen*, W. Davis*, D. Yee* & N. Zhang*

Event: 2001 International Symposium on VLSI Technology, Systems, and Applications. at Hsinchu, Taiwan

TL;DR: A design infrastructure which achieves this is described, which has a particular emphasis on methods for high level specification and estimation, that provides a fully automated chip design flow. (via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure (OpenAlex)
Sources: Web Of Science, ORCID
Added: July 9, 2022

Employment

Updated: November 12th, 2020 11:53

2015 - present

North Carolina State University Raleigh, North Carolina, US
Professor Electrical and Computer Engineering

2008 - 2015

North Carolina State University Raleigh, North Carolina, US
Associate Professor Electrical and Computer Engineering

2002 - 2008

North Carolina State University Raleigh, North Carolina, US
Assistant Professor Electrical and Computer Engineering

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