William Rhett Davis

A Virtual Platform for Object Detection Systems

2021 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC).

An Instruction-Level Power and Energy Model for the Rocket Chip Generator

2021 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED).

Bridging the Organization Gap for EDA Machine Learning Data

Kalafala, K., Fu, H., Davis, W. R., Aadithya, K., & Clevenger, L. A. (2021, August 16). Presented at the DesignCon.

Fast and Accurate PPA Modeling with Transfer Learning

2021 ACM/IEEE 3RD WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD).

Fast and Accurate PPA Modeling with Transfer Learning

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). Presented at the 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Munich, Germany.

FreePDK3: A Novel PDK for Physical Verification at the 3nm Node

Sadangi, S., Pasumarthy, V., Pitts, W. S., & Davis, W. R. (2021, May). Presented at the Synopsys Speaker Series.

System-Level Power Analysis with IEEE 2416 Power Models

Frenkil, J., Dhanwada, N., Davis, R., & Ratchkov, D. (2021, March 1). Workshop presented at the Design and Verification Conference and Exhibition (DVCON).

UPM/IEEE 2416 Power Modeling Standard: A Practitioner’s Perspective

Dhanwada, N., Davis, R., Dhanwada, N., & Frenkil, J. (2021, July 28). Embedded Tutorial presented at the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Views from the Cloud

Davis, W. R. (2021, August). Panel Discussion presented at the Si2 Annual Technical Forum.

A Gentle Introduction to the Open Model Interface for Reliability Simulations

Davis, W. R. (2020, April). Presented at the Si2 OpenAccess Live Forum.

An Industry-standard approach toward modeling device aging

Davis, W. R., & Shaw, C. (2020, April). Virtual session video presented at the International Reliability Physics Symposium.

Design Rule Checking with a CNN Based Feature Extractor

PROCEEDINGS OF THE 2020 ACM/IEEE 2ND WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD '20), pp. 9–14.

EDA Roadmap for Machine Learning & AI Standardization

Davis, W. R. (2020, January 30). EDA Roadmap for Machine Learning & AI Standardization. Panel Discussion, presented at the DesignCon, Santa Clara, CA.

How to write a compact reliability model with the Open Model Interface (OMI

2020 IEEE International Reliability Physics Symposium (IRPS). Presented at the 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX.

System Level Power Analysis with UPM

Baker, A., Davis, W. R., Dhanwada, N., Frenkil, J., & Ratchkov, D. (2020, July 20). Virtual tutorial presented at the Design Automation Conference (DAC).

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 66(2), 756–768.

Characterization of Fast, Accurate Leakage Power Models for IEEE P2416

20th International Symposium on Quality Electronic Design (ISQED). Presented at the 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA.

Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes

Bhanushali, K., & Davis, W. R. (2019, March 14). Presented at the Free Silicon Conference (FSiC).

Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools

20th International Symposium on Quality Electronic Design (ISQED). Presented at the 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA.

Is Your AI-based EDA Tool Production-Ready?

Davis, W. R. (2019, June 3). Panel discussion presented at the Design Automation Conference.

OpenAccess Partitions: How Fast Can We Go?

Davis, W. R. (2019, October). Presented at the Si2 OpenAccess Live Forum.

OpenAccess Partitions: How Fast Can We Go?

Davis, W. R. (2019, June 5). Presented at the Design Automation Conference, Las Vegas, NV.

Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages

2019 International 3D Systems Integration Conference (3DIC). Presented at the 2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan.

Physical Design of a Stacked Heterogeneous Multi-Core Processor

Davis, W. R. (2018, January). Presented at the ARM Research, Cambridge, UK.

H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor

2017 IEEE International Conference on Computer Design (ICCD), 145–152.

Physical Design of a Stacked Heterogeneous Multi-Core Processor

Davis, W. R. (2017, September 19). Presented at the Oxford Circuits and Systems Conference, Oxford, UK.

Novel packaging and thermal measurement for 3D heterogeneous stacks

2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM). Presented at the 2016 International Symposium on 3D Power Electronics Integration and Manufacturing, Raleigh, NC.

Physical Design of a 3D-Stacked Heterogeneous Multi-Core Processor

2016 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2016 IEEE International 3D Systems Integration Conference (3DIC), -San Francisco, CA.

Thermal raman and IR measurement of heterogeneous integration stacks

2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 1505–1510.

Computing in 3D

2015 International 3D Systems Integration Conference (3DIC). Presented at the 10.1109/3DIC.2015.7334571, Sendai, Japan.

FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology

In ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical Design (pp. 165–170).

Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks

2015 International 3D Systems Integration Conference (3DIC), 1–3.

Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4(11), 1862–1870.

Electrothermal Simulation of Three Dimensional Integrated Circuits

In R. Sharma (Ed.), Design of 3D Integrated Circuits and Systems. Boca Raton, FL: CRC Press.

Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC

2014 IEEE International Conference on IC Design & Technology. Presented at the 2014 IEEE International Conference on IC Design & Technology (ICICDT).

Thermal Pathfinding for 3-D ICs

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4(7), 1159–1168.

Towards a Standard Flow for System Level Power Modeling

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Presented at the 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA.

Applications and design styles for 3DIC

2013 IEEE International Electron Devices Meeting. Presented at the 2013 IEEE International Electron Devices Meeting, Washington, DC.

Design of controller for L2 cache mapped in Tezzaron stacked DRAM

2013 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA.

Exploring early design tradeoffs in 3DIC

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 545–549.

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

Rationale for a 3D heterogeneous multi-core processor

2013 IEEE 31st International Conference on Computer Design (ICCD), 154–168.

A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2(4), 660–667.

Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 68(2), 171–182.

Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels

IET Circuits, Devices & Systems, 6(1), 35.

Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(5), 676–689.

Leakage Power Contributor Modeling

IEEE DESIGN & TEST OF COMPUTERS, 29(2), 71–78.

Modeling Power Variability (from Small to Large

Davis, W. R. (2012, October 9). Presented at the Silicon Integration Inititative (Si2) Conference.

Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 31(10), 1522–1535.

Pathfinder 3D: A Flow for System-Level Design Space Exploration

2011 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan.

3D specific systems: Design and CAD

2011 Asian Test Symposium, 470–473.

Adaptive clock distribution for 3D integrated circuits

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 91–94.

An energy-efficient 64-QAM MIMO detector for emerging wireless standards

2011 Design, Automation & Test in Europe. Presented at the 2011 Design, Automation & Test in Europe, Grenoble, France.

Architecture, Design, and CAD for 3D-ICs

Davis, W. R. (2011, October). Presented at the Institute of Microelectronics, Agency for Science, Technology, and Research (A*STAR), Singapore.

Coordinating 3D designs: Interface IP, standards or free form?

2011 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan.

Design and Computer Aided Design of 3DIC

In A. Sheibanyrad, F. Pétrot, & A. Jantsch (Eds.), 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems (pp. 75–88).

Predictive Process Design Kits

In Y. Cao (Ed.), Predictive Technology Model for Robust Nanoelectronic Design. Integrated Circuits and Systems (pp. 121–140).

Test & Reliability Challenges in 3D NoCs

Davis, W. R. (2011, June 5). Test & Reliability Challenges in 3D NoCs. Presented at the Design Automation Conference (DAC) Workshop on Diagnostic Services in Networks-on-Chip: Test, Debug, & On-Line Monitoring.

Three-dimensional SRAM design with on-chip access time measurement

ELECTRONICS LETTERS, 47(8), 485–486.

A Low-Area Flexible MIMO Detector for WiFi/WiMAX Standards

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). Presented at the 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, Germany.

Algorithm and hardware complexity reduction techniques for k-best sphere decoders

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI, 471–476.

Creating 3D Specific Systems: Architecture, Design and CAD

International Symposium on Microelectronics, 2010(1), 23–27.

Creating 3D Specific Systems: Architecture, Design, and CAD

2010 Design, Automation & Test in Europe Conference & Exhibition, 1684–1688.

Investigation of tier-swapping to improve the thermal profile of memory-on-logic 3DICs

Melamed, S., Thorolfsson, T., Srinivasan, A., Cheng, E., Franzon, P., & Davis, W. R. (2010, October). Presented at the International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).

Low Power Hypercube Divided Memory FFT Engine Using 3D Integration

ACM Transactions on Design Automation of Electronic Systems, 16(1), 1–25.

Modeling Layout-Dependent Stress Effects: Opportunities for OpenDFM

Davis, W. R. (2010, June 13). Presented at the Design Automation Conference (DAC) Open Design-for-Manufacturability (OpenDFM) Workshop.

Thermal Adaptive Clock Design for 3D Integrated Circuits

Chen, X., & Davis, W. R. (2010, September 13). Presented at the Semiconductor Research Corporation (SRC) TECHCON.

Thermal analysis and verification of a mounted monolithic integrated circuit

Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon), 37–40.

Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 17(4), 496–506.

Automated Design Space Exploration for DSP Applications

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 56(2-3), 199–216.

Delay analysis and design exploration for 3D SRAM

2009 IEEE International Conference on 3d Systems Integration, 244–247.

High-Throughput Low-Complexity MIMO Detector Based on K-Best Algorithm

GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI, 451–456.

Junction-level thermal extraction and simulation of 3DICs

2009 IEEE International Conference on 3d Systems Integration, 395–401.

Parallel merge algorithm for high-throughput signal processing applications

ELECTRONICS LETTERS, 45(3), 188–189.

Prototyping in 3D-ICs: Design Flow Needs

Davis, W. R. (2009, October). Presented at the Silicon Integration Inititative (Si2) and Global Semiconductor Association (GSA) Workshop on Requirements for 3D Design Flow Interoperability Standards.

Save Your Energy: A Fast and Accurate Approach to NoC Power Estimation

Mineo, C., & Davis, W. R. (2009, February). Presented at the Workshop on 3D Integration and Interconnect-Centric Architectures (in conjunction with the International Symposium on High Performance Computer Architecture.

The Benefits of 3D Networks-on-Chip

Davis, W. R. (2009, December). Presented at the Silicon Integration Initiative (Si2) Low-Power Coalition Technical Steering Group Web-Meeting.

The Benefits of 3D networks-on-chip as shown with LDPC decoding

2009 IEEE International Conference on 3d Systems Integration, 89–96.

An 8192-point Fast Fourier Transform 3D-IC Case Study

2008 51st Midwest Symposium on Circuits and Systems, 438–441.

An Architecture Evaluator for Three-Dimensional Integrated Circuits

Davis, W. R. (2008, May). Presented at the Stanford University ECE Department Seminar.

An Efficient VLSI Implementation for the 1D Convolutional Discreet Wavelet Transform

2008 51st Midwest Symposium on Circuits and Systems. Presented at the 2008 51st Midwest Symposium on Circuits and Systems, Knoxville, TN.

Automation and Back-End Design within the FreePDK OpenAccess 45nm PDK and Cell Libraries for University Flows

Davis, W. R. (2008, June). Presented at the Semiconductor Research Corporation (SRC) e-Workshop.

Computer-Aided Design and Application Exploration for 3D Integrated Circuits

Proceedings of the Government Microcircuit Applications & Critical Technology (GOMACTech) Conference. Presented at the Government Microcircuit Applications & Critical Technology (GOMACTech) Conference.

Design and CAD for 3D Integrated Circuits

DAC '08: Proceedings of the 45th annual Design Automation Conference, 668–673.

FreePDK: A Free OpenAccess 45nm PDK and Cell Library for Universities

Davis, W. R. (2008, October). Presented at the Semiconductor Research Corporation (SRC) e-Workshop.

Inter-Die Signaling in Three Dimensional Integrated Circuits

2008 IEEE Custom Integrated Circuits Conference. Presented at the 008 IEEE Custom Integrated Circuits Conference, San Jose, CA.

3D Interconnect Device Design: Theory vs. Reality

Future Fab International, (23), 38–40.

3D-IC Design: Theory vs. Reality

Davis, W. R. (2007, June). Presented at the University of Utah ECE Department Seminar, Salt Lake City, UT.

An Architecture for Energy Efficient Sphere Decoding

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design, 244–249.

Design for 3D Integration and Applications

2007 International Symposium on Signals, Systems and Electronics, 263–266,

Designing FIFO Buffers using 3DIC Technology

VLSI Multilevel Interconnection (VMIC) Conference, 267–272.

Energy-Efficient Sphere Decoding (and other research efforts

Davis, W. R. (2007, September). Presented at the DARPA/OSD Trusted Foundry Circuit Designers Meeting, Essex Junction, VT.

FreePDK: An Open Source, OpenAccess Design Kit

Davis, W. R. (2007, November 5). Presented at the OpenAccess Conference.

FreePDK: An Open-Source Variation-Aware Design Kit

2007 IEEE International Conference on Microelectronic Systems Education (MSE'07). Presented at the 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), San Diego, CA.

Architecture for Energy Efficient Sphere Decoding

2006 IEEE International SOC Conference, 267–270.

Automated Architectural Exploration for Signal Processing Algorithms

In 2006 IEEE Workshop on Signal Processing Systems Design and Implementation (pp. 274–279,).

Breaking Rent’s Rule: Opportunities for 3D Interconnect Networks

VLSI Multilevel Interconnection (VMIC) Conference, 228–233.

Compact Electrothermal Modeling of an X-band MMIC

2006 IEEE MTT-S International Microwave Symposium Digest, 651–654.

Demystifying 3D ICs: The Pros and Cons of Going Vertical

Davis, W. R. (2006, April). Presented at the Virginia Tech ECE Department Seminar, Blacksburg, VA.

Exploring Compromises among Timing, Power and Temperature in Three-Dimensional Integrated Circuits

DAC '06: Proceedings of the 43rd annual Design Automation Conference, 997–1002.

Performance Trend in Three-Dimensional Integrated Circuits

2006 International Interconnect Technology Conference, 45–47.

Tool Integration for Signal Processing Architectural Exploration

Hourani, R., Jenkal, R., Davis, R., & Alexander, W. (2006, April). Presented at the Electronic Design Process (EDP) Workshop.

Demystifying 3D ICs: The procs and cons of going vertical

IEEE DESIGN & TEST OF COMPUTERS, 22(6), 498–510.

OpenAccess Tools for 3D Integration

Davis, W. R. (2005, November 10). Presented at the OpenAccess Conference, San Jose, CA.

Pre-route Net Classing for Crosstalk Avoidance

Hua, H., Sule, A., Mineo, C., & Davis, W. R. (2005, September 12). Presented at the Cadence Designer Network Live Conference (CDNLive), San Jose, CA.

Wire-Delay Reduction Analysis of a 3-Tier, 8-Point Fast Fourier Transform 3D-IC

VLSI Multilevel Interconnection (VMIC) Conference, 474–479.

Multi-Parameter Power Minimization of Synthesized Datapaths

IEEE Computer Society Annual Symposium on VLSI, 151–157.

500 Mb/s Soft Output Viterbi Decoder

IEEE Journal of Solid State Circuits, 38(7), 1234–1241.

Automated Design Flows for High-Performance Systems

Davis, W. R. (2003, February 11). Presented at the OpenAccess Conference, San Jose, CA.

Getting High-Performance Silicon from System-Level Design

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 238–243.

Real-Time System-on-a-Chip Emulation

In G. Martin & H. Chang (Eds.), Winning the SoC Revolution (pp. 229–253).

System-Level Design: Past, Present, and Future

Davis, W. R. (2003, February). Presented at the University of Tennessee ECE Department Seminar, Knoxville, TN.

500 Mb/s Soft Output Viterbi Decoder

European Solid-State Circuits Conference (ESSCIRC), 523–526,

A Design Environment for High-Throughput, Low-Power Dedicated Signal Processing Systems

IEEE Journal of Solid State Circuits, 37(3), 420–431.

A Hierarchical, Automated Design Flow for Low-Power, High-Throughput Digital Signal Processing IC’s

(PhD Thesis). Electrical Engineering Department, University of California, Berkeley.

Implementation of high throughput soft output viterbi decoders

IEEE Workshop on Signal Processing Systems, 146–151.

A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 545–548.

An Automated Design Flow for Low-Power, High-Throughput Dedicated Signal Processing Systems

Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, 475–480.

An Automated Design Flow for Low-Power, High-Throughput Dedicated Signal Processing Systems

Davis, W. R. (2001, December). Presented at the MathWorks, Inc. seminar Innovation First: System Level Design for DSP and Communications, Waltham, MA.

Design Technology for Low Power Radio Systems

Davis, W. R. (2001, September). Presented at the Computer Aided Network Design Workshop (CANDE), Grand Teton, WY.

Wireless systems-on-a-chip design

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers, 45–48.