@article{kim_gloster_alexander_2017, title={An Acceleration Framework for Synthetic Aperture Radar Algorithms}, volume={10201}, ISBN={["978-1-5106-0904-4"]}, ISSN={["1996-756X"]}, DOI={10.1117/12.2261397}, abstractNote={Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to oﬀ-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration oﬀered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.}, journal={ALGORITHMS FOR SYNTHETIC APERTURE RADAR IMAGERY XXIV}, author={Kim, Youngsoo and Gloster, Clay S. and Alexander, Winser E.}, year={2017} }
@article{alexander_williams_2017, title={Design of digital filters}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={205–275} }
@article{alexander_williams_2017, title={Digital signal processing systems design}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={455–517} }
@article{alexander_williams_2017, title={Digital signal processing: principles, algorithms and system design preface}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={XXVII-} }
@article{alexander_williams_alexander_williams_2017, title={Finite Word Length Effects}, ISBN={["978-0-12-804547-3"]}, DOI={10.1016/b978-0-12-804547-3.00006-1}, abstractNote={Chapter 6 covers methods used to represent numbers and the impact of the use of finite precision arithmetic for the implementation of discrete time systems. It discusses the representation of numbers using the IEEE floating point representation, computational errors due to rounding, and the multiplication of numbers that are represented using floating point. It covers the analytical basis for the two's complement representation of numbers and computational procedures for numbers represented using two's complement numbers. It covers the scaling of the coefficients for discrete time systems for given word sizes and for a restriction to avoid over ow during computations. It also presents a concept for statistical analysis of rounding errors due to word length effects.}, journal={DIGITAL SIGNAL PROCESSING: PRINCIPLES, ALGORITHMS AND SYSTEM DESIGN}, author={Alexander, Winser E. and Williams, Cranos M. and Alexander, WE and Williams, CM}, year={2017}, pages={351–388} }
@article{alexander_williams_2017, title={Frequency domain analysis}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={159–204} }
@article{alexander_williams_2017, title={Fundamental DSP concepts}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={19–157} }
@article{alexander_williams_2017, title={Hardware implementation}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={519–561} }
@article{alexander_williams_2017, title={Implementation of discrete time systems}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={277–350} }
@article{alexander_williams_2017, title={Introduction to digital signal processing}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={1–17} }
@article{alexander_williams_2017, title={Multirate digital signal processing}, journal={Digital Signal Processing: Principles, Algorithms and System Design}, author={Alexander, W. E. and Williams, C. M.}, year={2017}, pages={389–454} }
@article{kim_alexander_edmonson_2012, title={A Dataflow Framework for DSP Algorithm Refinement}, DOI={10.1109/isvlsi.2012.74}, abstractNote={Current video compression algorithms are increasingly complicated and difficult to analyze and profile. Design tools and system level languages often prove to be inefficient and incapable of providing complexity analysis as a first step directed toward at the implementation of video compression algorithms. This paper proposes framework that will help to develop a methodology that facilitates the derivation of analytical dataflow models. The framework proposes dataflow models for quantifying the underlying algorithm's memory complexity, related timing considerations, and verification of the correctness of the video compression algorithm.}, journal={2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)}, author={Kim, Youngsoo and Alexander, Winser E. and Edmonson, William W.}, year={2012}, pages={1-+} }
@article{hourani_jenkal_davis_alexander_2009, title={Automated Design Space Exploration for DSP Applications}, volume={56}, ISSN={["1939-8115"]}, DOI={10.1007/s11265-008-0226-2}, number={2-3}, journal={JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY}, author={Hourani, Ramsey and Jenkal, Ravi and Davis, W. Rhett and Alexander, Winser}, year={2009}, month={Sep}, pages={199–216} }
@article{xing_bitzer_alexander_vouk_stomp_2009, title={Identification of protein-coding sequences using the hybridization of 18S rRNA and mRNA during translation}, volume={37}, ISSN={["1362-4962"]}, DOI={10.1093/nar/gkn917}, abstractNote={We introduce a new approach in this article to distinguish protein-coding sequences from non-coding sequences utilizing a period-3, free energy signal that arises from the interactions of the 3′-terminal nucleotides of the 18S rRNA with mRNA. We extracted the special features of the amplitude and the phase of the period-3 signal in protein-coding regions, which is not found in non-coding regions, and used them to distinguish protein-coding sequences from non-coding sequences. We tested on all the experimental genes from Saccharomyces cerevisiae and Schizosaccharomyces pombe. The identification was consistent with the corresponding information from GenBank, and produced better performance compared to existing methods that use a period-3 signal. The primary tests on some fly, mouse and human genes suggests that our method is applicable to higher eukaryotic genes. The tests on pseudogenes indicated that most pseudogenes have no period-3 signal. Some exploration of the 3′-tail of 18S rRNA and pattern analysis of protein-coding sequences supported further our assumption that the 3′-tail of 18S rRNA has a role of synchronization throughout translation elongation process. This, in turn, can be utilized for the identification of protein-coding sequences.}, number={2}, journal={NUCLEIC ACIDS RESEARCH}, author={Xing, Chuanhua and Bitzer, Donald L. and Alexander, Winser E. and Vouk, Mladen A. and Stomp, Anne-Marie}, year={2009}, month={Feb}, pages={591–601} }
@article{alexander_reeves_gloster_2000, title={Parallel image processing with the block data parallel architecture (Reprinted from Proceedings of the IEEE, vol 84, pg 947-968, 1996)}, volume={44}, ISSN={["0018-8646"]}, DOI={10.1147/rd.445.0681}, abstractNote={Many digital signal and image processing algorithms can be speeded up by executing them in parallel on multiple processors. The speed of parallel execution is limited by the need for communication and synchronization between processors. In this paper, we present a paradigm for parallel processing that we call the block data flow paradigm (BDFP). The goal of this paradigm is to reduce interprocessor communication, and relax the synchronization requirements for such applications. We present the block data parallel architecture which implements this paradigm, and we present methods for mapping algorithms onto this architecture. We illustrate this methodology for several applications including two-dimensional (2-D) digital filters, the 2-D discrete cosine transform, QR decomposition of a matrix, and Cholesky factorization of a matrix. We analyze the resulting system performance for these applications with regard to speedup and efficiency as the number of processors increases. Our results demonstrate that the block data parallel architecture is a flexible, high-performance solution for numerous digital signal and image processing algorithms.}, number={5}, journal={IBM JOURNAL OF RESEARCH AND DEVELOPMENT}, author={Alexander, WE and Reeves, DS and Gloster, CS}, year={2000}, month={Sep}, pages={681–702} }
@article{wu_ybarra_alexander_1998, title={A complex optimal signal-processing algorithm for frequency-stepped CW data}, volume={45}, ISSN={["1057-7130"]}, DOI={10.1109/82.686697}, abstractNote={We derive a complex nonlinear optimal signal-processing algorithm for estimating target ranges from a set of frequency-stepped continuous wave (FSCW) measurements. It is a generalization of a prior optimization algorithm in that the reflection amplitudes are modeled as phasors rather than real-valued scalars. The algorithm solves this nonlinear problem by separating it into its linear and nonlinear parts. The amplitudes of the reflections are first optimized by solving a set of linear equations in the least-squares sense. A performance measure is then calculated and scanned to find its global minimum to yield a set of reflection amplitudes and time-delay estimates. We derive analytical expressions for the performance measure and for the effects of noise in the measurement data. Finally, we present experimental results to demonstrate the performance of our algorithm.}, number={6}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING}, author={Wu, SKM and Ybarra, GA and Alexander, WE}, year={1998}, month={Jun}, pages={754–757} }
@article{sohn_kim_alexander_1998, title={A mean field annealing approach to robust corner detection}, volume={28}, ISSN={["1083-4419"]}, DOI={10.1109/3477.658581}, abstractNote={This paper is an extension of our previous paper to improve the capability of detecting corners. We proposed a method of boundary smoothing for curvature estimation using a constrained regularization technique in the previous paper. We propose another approach to boundary smoothing for curvature estimation in this paper to improve the capability of detecting corners. The method is based on a minimization strategy known as mean field annealing which is a deterministic approximation to simulated annealing. It removes the noise while preserving corners very well. Thus, we can detect corners easier and better in this approach than in the constrained regularization approach. Finally, some matching results based on the corners detected by corner sharpness in the mean field annealing approach are presented as a demonstration of the power of the proposed algorithm.}, number={1}, journal={IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS PART B-CYBERNETICS}, author={Sohn, K and Kim, JH and Alexander, WE}, year={1998}, month={Feb}, pages={82–90} }
@article{yoon_kim_alexander_park_sohn_1998, title={An optimum solution for scale-invariant object recognition based on the multiresolution approximation}, volume={31}, ISSN={["0031-3203"]}, DOI={10.1016/S0031-3203(97)00111-8}, abstractNote={This paper presents a multiresolution approximation approach to obtaining boundary representations for object recognition. Our technique combines a multiresolution approximation and the curvature scale-space representation for obtaining representations. Our research consists of two main parts. In the first part of our research, we introduce the continuous multiresolution approximation (CMA) in terms of the continuous wavelet transform (CWT). Then we implement a fast algorithm to compute the CMA. We apply the CMA to a boundary to obtain approximations of the boundary at various resolutions. The CMA provides a consistent interpretation of objects with scale-variations. Moreover, we can quickly compute our representations by using the fast algorithm for the CMA. In the second part, we propose three representations for object recognition which cover most boundary-based object recognition problems. All three representations use the approximations obtained by the CMA. Each representation has different features and covers different types of matching problems but all representations are constructed by using curvature zero crossings of the approximations. Our representations provide a general but reliable solution to most boundary based object matching problems. Finally, we investigate the properties of our representations such as validity, efficiency, and reliability. We verified our results experimentally to demonstrate the feasibility of using our representations for object recognition.}, number={7}, journal={PATTERN RECOGNITION}, author={Yoon, SH and Kim, JH and Alexander, WE and Park, SM and Sohn, KH}, year={1998}, month={Jul}, pages={889–908} }