@article{bhanushali_zhao_pitts_franzon_2021, title={A 125 mu m x 245 mu m Mainly Digital UHF EPC Gen2 Compatible RFID Tag in 55 nm CMOS Process}, volume={5}, ISSN={["2469-7281"]}, DOI={10.1109/JRFID.2021.3087448}, abstractNote={This paper presents a compact and largely digital UHF EPC Gen2-compatible RFID implemented using digital IP blocks that are easily portable. This is the first demonstration of a digital Gen2-compatible RFID tag chip with an area of $125{\mu }\text{m} \times 245{\mu }\text{m}$ and −2 dBm sensitivity operating in the 860–960MHz band. It is enabled by a) largely standard cell-based digital implementation using dual-phase RF-only logic approach, b) near-threshold voltage operation, and c) elimination of area intensive, complex, and less scalable rectifiers, storage capacitors, and power management units used in conventional RFID tags. In this demonstration, all but six cells were directly used from the standard cell library provided by the foundry. This makes it suitable for cost-sensitive applications, and as embedded RFIDs for tagging counterfeit Integrated Circuits (ICs).}, number={3}, journal={IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION}, author={Bhanushali, Kirti and Zhao, Wenxu and Pitts, W. Shepherd and Franzon, Paul D.}, year={2021}, month={Sep}, pages={317–323} }
 @article{nigussie_pan_lipa_pitts_delacruz_franzon_2021, title={Design Benefits of Hybrid Bonding for 3D Integration}, ISSN={["2377-5726"]}, DOI={10.1109/ECTC32696.2021.00296}, abstractNote={We present electrical and thermal analyses of 3D digital designs using hybrid bonding, specifically using the design rules, and other properties, for the XPERI DBI® technology at a $\mathrm{1.6}\ \mu \mathrm{m}$ pad pitch. We also go over the advantages of hybrid bonding over thermo-compression bonding (TCB) and 2D designs. Commercial 3D physical design tools were not mature when we did this work, so we came up with a methodology that builds on 2D tools. Our design flow includes scripts for optimal assignment of bonding locations, partitioning of netlist and delay constraints, and optimization techniques that involve iterating on delay constraints. Various partitioning schemes that include targeting long nets, managing flip-flop distribution between tiers, and minimum cut partitioning using an open source tool were analyzed. Because analysis results could vary from design to design, we propose potential metrics that can be used to identify designs that may benefit from 3DIC technology. Analysis results showed that we were able to reduce routed wire length by up to 57%. Logic power and total power decreased by up to 34% and 22% respectively. Silicon area also improved by 11%.11This work was supported, in part, by Xperi. DISTRIBUTION STATE-MENT A. Approved for public release: distribution unlimited.}, journal={IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021)}, author={Nigussie, Theodros and Pan, Tse-Han and Lipa, Steve and Pitts, W. Shepherd and DeLaCruz, Javi and Franzon, Paul}, year={2021}, pages={1876–1881} }
 @article{kashyap_pitts_baron_wong_wu_franzon_2021, title={High Speed Receiver Modeling Using Generative Adversarial Networks}, ISSN={["2165-4107"]}, DOI={10.1109/EPEPS51341.2021.9609124}, abstractNote={This paper presents a generative approach to modeling a high-speed receiver with a time series input. The model is not built with domain knowledge but learned from a wide range of channel conditions and input bitstreams to generate an eye diagram. The generated eye diagrams are similar to the simulated eye diagrams for the same scenario. We also developed a neural network model to evaluate the generated eye diagram's relevant characteristics, such as eye height and width. The generated eye diagrams are within 7% and 3% error to the ground-truth in eye height and eye width, respectively, based on our evaluation neural network.}, journal={IEEE 30TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS 2021)}, author={Kashyap, Priyank and Pitts, W. Shepherd and Baron, Dror and Wong, Chau-Wai and Wu, Tianfu and Franzon, Paul D.}, year={2021} }
 @article{sarkar_mills_lee_pitts_misra_franzon_2018, title={On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process}, volume={47}, ISSN={["1543-186X"]}, DOI={10.1007/s11664-017-5914-x}, number={2}, journal={JOURNAL OF ELECTRONIC MATERIALS}, author={Sarkar, Biplab and Mills, Steven and Lee, Bongmook and Pitts, W. Shepherd and Misra, Veena and Franzon, Paul D.}, year={2018}, month={Feb}, pages={994–997} }
 @article{schinke_priyadarshi_pitts_di spigna_franzon_2011, title={SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation}, volume={5}, ISSN={["1751-858X"]}, DOI={10.1049/iet-cds.2010.0410}, abstractNote={The majority of nanocrystal floating gate research has been done at the device level. Circuit-level research is still in its early stages because of the lack of a physical device model appropriate for circuit simulations. In this study, a comprehensive and accurate SPICE-compatible physical equation-based model of nanocrystal floating gate devices is developed based on uniform direct tunnelling and Fowler-Nordheim tunnelling. The main contribution is a Verilog-A module that captures the physical behaviours of programming and erasing the device. A predictive NMOS model is then used for modelling the conduction channel to determine the behavioural I - V characteristics. The proposed model uses only explicit formulae resulting in fast computation appropriate for circuit simulation and can be used in any SPICE simulator supporting Verilog-A. It interacts dynamically with the rest of the circuit and includes charge leakage which enables power consumption analysis. The simulation results of the proposed model fit well to experimental results of various fabricated devices. Additionally, it is verified in HSPICE, demonstrating a significant speedup and good agreement with a numerical device simulator. This study is important in bridging the gap between device- and circuit-level research.}, number={6}, journal={IET CIRCUITS DEVICES & SYSTEMS}, author={Schinke, D. and Priyadarshi, S. and Pitts, W. Shepherd and Di Spigna, N. and Franzon, P.}, year={2011}, month={Nov}, pages={477–483} }
 @article{gupta_snyder_pitts_2010, title={Concurrent visual multiple lane detection for autonomous vehicles}, ISSN={["2577-087X"]}, DOI={10.1109/robot.2010.5509389}, abstractNote={This paper proposes a monocular vision solution to simultaneous detection of multiple lanes in navigable regions / urban roads using accumulator voting. Unlike other approaches in literature, this paper first examines the extent of lane parameters required for continuous control of any vehicle manually or autonomously. The accumulator-based algorithm is designed using this fundamental control knowledge to vote for the required lane parameters (position of lanes and steering angle required) in the image plane. The novel accumulator voting scheme is called “Parametric Transform for Multi-lane Detection.” This paper not only adapts predictive control in the image plane, but also detects multiple lanes in the scene concurrently in the form of multiple peaks in the accumulator. This method is robust to shadows and invariant to color, texture, and width of the road. Finally, the method is designed for dashed/continuous lines.}, journal={2010 IEEE INTERNATIONAL CONFERENCE ON ROBOTICS AND AUTOMATION (ICRA)}, author={Gupta, Rachana Ashok and Snyder, Wesley and Pitts, W. Shepherd}, year={2010}, pages={2416–2422} }