@article{chen_zhu_davis_franzon_2014, title={Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits}, volume={4}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2014.2361356}, abstractNote={In this paper, we present novel techniques to handle the complexity and challenges in clock distribution for 3-D integrated circuit. First, we propose a novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry. The new deskew technique neither relies on an accurate through-silicon-vias model nor an accurate reference clock distribution. Second, we design a phase-mixer-based tunable-delay-buffer (TDB), which can be linearly tuned in 360° and tolerant to process-voltage-termperature (PVT) variations. Third, based on the new deskew technique and TDB design, we propose an efficient clock distribution network topology, which can be realized without a need of balanced H-tree. Moreover, a thermal profile-based optimization flow is developed to further improve the power efficiency and reduce design overhead. A case study shows that the proposed techniques are able to largely improve the clock skews. The optimization flow is capable of reducing the design cost to achieve a better tradeoff of the skew performance and the design overhead.}, number={11}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Chen, Xi and Zhu, Ting and Davis, William Rhett and Franzon, Paul D.}, year={2014}, month={Nov}, pages={1862–1870} }
 @inproceedings{chen_davis_franzon_2011, title={Adaptive clock distribution for 3D integrated circuits}, DOI={10.1109/epeps.2011.6100195}, abstractNote={Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many challenges. In this work, we present new techniques for realizing highly adaptive and reliable clock distribution for 3D ICs. Firstly, an efficient clock distribution topology without need of balanced H-tree is proposed. Secondly, a robust tunable-delay-buffer (TDB) circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry. Moreover, a design optimization flow is constructed for improving the adaptive clock design based on the thermal profiles. Experiment results show that the clock skews are significantly reduced using the proposed techniques.}, booktitle={2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems}, author={Chen, X. and Davis, W. R. and Franzon, P. D.}, year={2011}, pages={91–94} }