Works (9)

Updated: July 5th, 2023 15:58

2010 journal article

A functional unit and register binding algorithm for interconnect reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(4), 641–646.

By: T. Kim & X. Liu

Source: NC State University Libraries
Added: August 6, 2018

2010 conference paper

case study: gpu-based implementation of sequence pair based floorplanning using cuda

2010 ieee international symposium on circuits and systems, 917–920.

By: W. Choi & X. Liu

Source: NC State University Libraries
Added: August 6, 2018

2009 journal article

Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 17(11), 1593–1601.

By: Z. Yu n & X. Liu n

author keywords: Clock distribution; low power; timing; VLSI
TL;DR: This paper presents the first rotary-clock-based nontrivial digital circuit, a low-power and high-speed finite-impulse response (FIR) filter, which uses the spatially distributed multiple clock phases of rotary clock and achieves high power savings. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: August 6, 2018

2007 journal article

Low-power rotary clock array design

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 15(1), 5–12.

By: Z. Yu n & X. Liu n

author keywords: clocks; partial element equivalent circuit; synchronization; transmission line resonators; traveling-wave amplifiers
TL;DR: This paper has developed a software tool based on the method of partial element equivalent circuit that is capable of extracting the SPICE netlist from the layout specification of a rotary clock design and proposes a power minimization algorithm. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: August 6, 2018

2006 journal article

An efficient low-power repeater-insertion scheme

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 25(12), 2726–2736.

By: Y. Peng n & X. Liu n

author keywords: interconnect; low-power; repeater
TL;DR: The problem of runtime reduction for low-power repeater insertion is investigated and a novel repeater-insertion algorithm based on the Lagrangian relaxation framework is proposed, which is capable of producing high-quality solutions at a very fast speed and without manual tuning of the algorithm parameters. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

2005 journal article

HyPE: Hybrid power estimation for IP-based systems-on-chip

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 24(7), 1089–1103.

By: X. Liu n & M. Papaefthymiou*

author keywords: design automation; optimization; power model; signal statistics
TL;DR: A novel power estimation scheme for programmable systems consisting of predesigned datapath and memory components that yields highly accurate estimates within short runtimes by combining high-level simulation with analytical macromodeling of circuit characteristics. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

2005 journal article

Practical repeater insertion for low power: What repeater library do we need?

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 25(5), 917–924.

By: X. Liu, Y. Peng & M. Papaefthyrniou

author keywords: interconnect; repeater insertion low power
Source: Web Of Science
Added: August 6, 2018

2004 journal article

A Markov chain sequence generator for power macromodeling

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 23(7), 1048–1062.

By: X. Liu n & M. Papaefthymiou*

author keywords: power estimation; power model; signal statistics; vector generation
Source: Web Of Science
Added: August 6, 2018

2003 journal article

Design of a 20-Mb/s 256-state Viterbi decoder

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 11(6), 965–975.

By: X. Liu n & M. Papaefthymiou*

author keywords: bus reduction; communications; data transfer; low power; pipelining
TL;DR: This paper proposes a data transfer oriented design methodology to implement a low-power 256-state rate-1/3 Viterbi decoder and applies precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: August 6, 2018

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