@article{yu_liu_2009, title={Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter}, volume={17}, ISSN={["1557-9999"]}, DOI={10.1109/TVLSI.2008.2006477}, abstractNote={Rotary clock is a resonant clocking technique that delivers on-chip clock signal distribution with very low power dissipation. Since it can only generate clock signals with multiple phases that are spatially distributed, rotary clock is often considered not applicable to industrial very large scale integration (VLSI) designs. This paper presents the first rotary-clock-based nontrivial digital circuit. Our design, a low-power and high-speed finite-impulse response (FIR) filter, is fully digital and generated using CMOS standard cells in 0.18 mum technology. We have shown that the proposed FIR filter is seamlessly integrated with the rotary clock technique. It uses the spatially distributed multiple clock phases of rotary clock and achieves high power savings. Simulation results demonstrate that our rotary-clock-based FIR filter can operate successfully at 610 MHz, providing a throughput of 39 Gb/s. In comparison with the conventional clock-tree-based design, our design achieves a 34.6% clocking power saving and a 12.8% overall circuit power saving. In addition, the peak current consumed by the rotary-clock-based filter is substantially lower by 40% on the average. Our study makes the crucial step toward the application of rotary clock technique to a broad range of VLSI designs.}, number={11}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Yu, Zhengtao and Liu, Xun}, year={2009}, month={Nov}, pages={1593–1601} }
 @article{yu_liu_2007, title={Low-power rotary clock array design}, volume={15}, ISSN={["1557-9999"]}, DOI={10.1109/TVLSI.2006.887804}, abstractNote={Rotary clock is a recently proposed clock distribution technique based on wave propagation in transmission lines. In this paper, we investigate the problem of power minimization of rotary clock designs. Specifically, we have developed a software tool based on the method of partial element equivalent circuit that is capable of extracting the SPICE netlist from the layout specification of a rotary clock design. Using our tool, we have performed extensive analysis that links various design parameters of a rotary clock design to its oscillation frequency and power dissipation. Based on the results of our analysis, we then propose a power minimization algorithm. Our algorithm derives a rotary clock structure that dissipates the minimal power while satisfying the clock dimension requirement and oscillating at the target frequency with the given clock load. Experimental results have demonstrated that, for target operating frequencies ranging from 0.5 to 5 GHz, rotary clock designs can achieve power savings of up to 80% in comparison with conventional clock tree implementations}, number={1}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Yu, Zhengtao and Liu, Xun}, year={2007}, month={Jan}, pages={5–12} }