2021 journal article
Eliminating Repetitive Short-Circuit Degradation and Failure of 1.2-kV SiC Power MOSFETs
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 9(6), 6773–6779.
author keywords: MOSFET; Silicon carbide; Silicon; Stress; Logic gates; Topology; Temperature measurement; Baliga Short-Circuit Improvement Concept (BaSIC) topology; depletion-mode MOSFET (DMM); power MOSFET; semiconductor device reliability; short-circuit (SC) currents
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(Web of Science)
Source: Web Of Science
Added: December 20, 2021
Silicon carbide (SiC) power MOSFETs are known to degrade and eventually fail under repetitive short-circuit (SC) stress. In this article, a new approach, named Baliga Short-Circuit Improvement Concept (BaSIC) depletion-mode MOSFET (DMM), is demonstrated to prevent the degradation and failure of 1.2-kV SiC power MOSFETs under repetitive SC stress. The new concept utilizes a low-voltage, gate–source-shorted Si DMM connected to the source of the SiC MOSFET. It was experimentally verified that no degradation or failure of the SiC power MOSFET occurs after over 3000 SC events with the BaSIC(DMM) topology while the SiC power MOSFETs degraded and failed after 200 SC events without it.