Emerging shared memory accelerator interfaces promote a tighter coupling between traditional general-purpose processing cores and accelerator units through cache-coherence and shared virtual address space capabilities. However, different interface standards solving similar problems often require custom designs and optimizations depending on the adopted interface. This work introduces CAPI-Precis, an abstract layer between CAPI, a cache-coherent interface standard proposed by IBM, and the Accelerator Functional Unit (AFU). CAPI-Precis provides a Compute-Centric FIFO-based paradigm with the shared memory accelerator interface, hiding CAPI complexities and latency requirements in an abstract layer focusing on optimized, efficient, and scalable AFUs. Such a layer adapts to other shared memory interfaces, such as CCIX or CXL, with minimal overhead in area and performance while preserving the algorithm logic design.