2012 journal article

FABSCALAR: AUTOMATING SUPERSCALAR CORE DESIGN

IEEE MICRO, 32(3), 48–59.

By: N. Choudhary n, S. Wadhavkar n, T. Shah n, H. Mayukh n, J. Gandhi n, B. Dwiel n, S. Navada n, H. Najaf-Abadi n, E. Rotenberg n

TL;DR: FabScalar aims to automate superscalar core design, opening up processor design to microarchitectural diversity and its many opportunities. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: August 6, 2018

2011 journal article

FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22.

By: N. Choudhary n, S. Wadhavkar n, T. Shah*, H. Mayukh*, J. Gandhi*, B. Dwiel n, S. Navada n, H. Najaf-abadi*, E. Rotenberg n

TL;DR: From this idea, a toolset is developed, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template, which defines canonical pipeline stages and interfaces among them. (via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018

Citation Index includes data from a number of different sources. If you have questions about the sources of data in the Citation Index or need a set of data which is free to re-distribute, please contact us.

Certain data included herein are derived from the Web of Science© and InCites© (2024) of Clarivate Analytics. All rights reserved. You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.