Yi-Der Wu

Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress

MICROELECTRONICS RELIABILITY, 44(2), 207–212.

Structural dependence of breakdown characteristics and electrical degradation in ultrathin RPECVD oxide/nitride gate dielectrics under constant voltage stress

SOLID-STATE ELECTRONICS, 47(1), 71–76.

1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process

IEEE ELECTRON DEVICE LETTERS, 21(3), 116–118.

The performance and reliability of PMOSFET's with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si-SiO2 interfaces prepared by remote plasma enhanced CVD and post-deposition rapid thermal annealing

IEEE TRANSACTIONS ON ELECTRON DEVICES, 47(7), 1361–1369.

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (< 2.0 nm) single layer and dual layer gate oxides

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (< 2.0 nm) single layer and dual layer gate oxides. MICROELECTRONICS RELIABILITY, 40(12), 1987–1995.

Bonding constraints and defect formation at interfaces between crystalline silicon and advanced single layer and composite gate dielectrics

APPLIED PHYSICS LETTERS, 74(14), 2005–2007.

Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides

IEEE ELECTRON DEVICE LETTERS, 20(6), 262–264.

Optimization of nitrided gate dielectrics by plasma-assisted and rapid thermal processing

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, Vol. 16, pp. 1721–1729.

Ultrathin nitride/oxide (N/O) gate dielectrics for p(+)-polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced CVD thermal oxidation process

IEEE ELECTRON DEVICE LETTERS, 19(10), 367–369.