Sumon Dey

Works (8)

Updated: April 11th, 2023 10:13

2022 article

FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS

2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022), pp. 113–121.

By: A. Gajjar n, P. Kashyap n , A. Aysu n, P. Franzon n , S. Dey* & C. Cheng *

TL;DR: An FPGA-based XGBoost accelerator designed with High-Level Synthesis (HLS) tools and design flow accelerating binary classification inference is showcased, showing a latency speedup of the proposed design over state-of-art CPU and GPU implementations, including energy efficiency and cost-effectiveness. (via Semantic Scholar)
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UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, NC State University Libraries, ORCID
Added: October 11, 2022

2022 article

Modeling of Adaptive Receiver Performance Using Generative Adversarial Networks

IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022), pp. 1958–1963.

By: P. Kashyap n , Y. Choi *, S. Dey*, D. Baron n , C. Wong n , T. Wu n , C. Cheng *, P. Franzon n 

author keywords: SerDes; receiver; behavior modeling; adaptive; generative; GAN; DFE; IBIS-AMI
TL;DR: A data-driven approach to modeling a high-speed serializer/deserializer (SerDes) receiver through generative adversarial networks (GANs) through the use of a discriminator structure that improves the training to generate a contour plot that makes it difficult to distinguish the ground truth. (via Semantic Scholar)
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UN Sustainable Development Goal Categories
10. Reduced Inequalities (OpenAlex)
Sources: Web Of Science, NC State University Libraries, ORCID
Added: September 19, 2022

2021 journal article

A Scalable Cluster-based Hierarchical Hardware Accelerator for a Cortically Inspired Algorithm

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 17(4).

By: S. Dey n, L. Baker n, J. Schabel  n, W. Li n & P. Franzon n 

author keywords: Neuromorphic computing; accelerator; cortical processor; hierarchical temporal memory; sparse distributed memory
TL;DR: A scalable, configurable and cluster-based hierarchical hardware accelerator through custom hardware architecture for Sparsey, a cortical learning algorithm inspired by the operation of the human cortex that uses a Sparse Distributed Representation to enable unsupervised learning and inference in the same algorithm. (via Semantic Scholar)
UN Sustainable Development Goals Color Wheel
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, NC State University Libraries
Added: February 28, 2022

2021 article

Design for 3D Stacked Circuits

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM).

By: P. Franzon n , W. Davis n, E. Rotenberg n, J. Stevens n, S. Lipa n, T. Nigussie n, H. Pan  n, L. Baker n ...

TL;DR: 2.5D and 3D technologies can give rise to a node equivalent of scaling due to improved connectivity because of improved connectivity, but design issues that need to be addressed in pursuing such exploitations include thermal management, design for test and computer aided design. (via Semantic Scholar)
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UN Sustainable Development Goal Categories
Sources: Web Of Science, NC State University Libraries
Added: July 11, 2022

2021 journal article

Hardware Implementation of Hierarchical Temporal Memory Algorithm

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 18(1).

By: W. Li n, P. Franzon n , S. Dey n & J. Schabel  n

author keywords: Hierarchical temporal memory (HTM); ASIC design; distributed memory; KTH benchmark
TL;DR: Hierarchical temporal memory is an un-supervised machine learning algorithm that can learn both spatial and temporal information of input that has been successfully applied to multiple areas. (via Semantic Scholar)
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Source: Web Of Science
Added: January 23, 2023

conference paper

Design and ASIC acceleration of cortical algorithm for text recognition

Dey, S., & Franzon, P. D. 2016 29th IEEE International System-on-Chip Conference (SOCC), 114–119.

By: S. Dey & P. Franzon 

Source: NC State University Libraries
Added: August 6, 2018

conference paper

Design and ASIC acceleration of cortical algorithm for text recognition

Dey, S., & Franzon, P. D. 2016 29th IEEE International System-on-Chip Conference (SOCC), 114–119.

By: S. Dey & P. Franzon 

Source: NC State University Libraries
Added: August 6, 2018

conference paper

Processor-in-memory support for artificial neural networks

Schabel, J., Baker, L., Dey, S., Li, W. F., & Franzon, P. D. 2016 IEEE International Conference on Rebooting Computing (icrc).

By: J. Schabel, L. Baker, S. Dey, W. Li & P. Franzon 

Source: NC State University Libraries
Added: August 6, 2018

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