Khaled Zakaria Ahmed

A two-dimensional numerical simulation of pulsed drain current transients in weak inversion and application to interface trap characterization on small geometry MOSFETs with ultrathin oxides

IEEE TRANSACTIONS ON ELECTRON DEVICES, 47(11), 2236–2237.

Analytic model of parasitic capacitance attenuation in CMOS devices with hyper-thin oxides

ELECTRONICS LETTERS, 36(20), 1699–1700.

Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime

IEEE TRANSACTIONS ON ELECTRON DEVICES, 47(7), 1349–1354.

Limitations of the modified shift-and-ratio technique for extraction of the bias dependence of L-eff and R-sd of LDD MOSFET's

IEEE TRANSACTIONS ON ELECTRON DEVICES, 47(4), 891–895.

Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors

IEEE ELECTRON DEVICE LETTERS, 20(4), 179–181.

Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-angstrom gate oxide MOSFET's

IEEE TRANSACTIONS ON ELECTRON DEVICES, 46(8), 1650–1655.

Modeled tunnel currents for high dielectric constant dielectrics

IEEE TRANSACTIONS ON ELECTRON DEVICES, 45(6), 1350–1355.