Kashyap Bellur

Low parasitic resistance contacts for scaled ULSI devices

Thin Solid Films, 332(1-2), 428–436.

Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors

Journal of the Electrochemical Society, 145(6), 2131–2137.

A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy

ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 571–585. Pennington, NJ: Electrochemical Society.

A comparative study of N+/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors

Journal of the Electrochemical Society, 144(10), 3659–3664.

Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology

ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 587–597. Pennington, NJ: Electrochemical Society.

The effect of the elevated source/drain doping profile on performance and reliability of deep submicron MOSFET's

IEEE Transactions on Electron Devices, 44(9), 1491–1498.

Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition

Rapid thermal and integrated processing V: Symposium held April 8-12, 1996, San Francisco, California, U.S.A. (Materials Research Society symposium; 429), 343–347.