Electrical & Computer Engineering

Detecting global stride locality in value streams

30th Annual International Symposium on Computer Architecture, 2003. Proceedings. Presented at the ISCA 2003: 30th International Symposium on Computer Architecture.

Dual-core execution: building a highly scalable single-thread instruction window

14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05). Presented at the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05).

Study of global frequency dynamic behavior of large power systems

IEEE PES Power Systems Conference and Exposition, 2004. Presented at the IEEE PES Power Systems Conference and Exposition, 2004.

Large scale storm outage management

IEEE Power Engineering Society General Meeting, 2004. Presented at the 2004 IEEE Power Engineering Society General Meeting.

Automated Testing Of Solid-State Watthour Meters In The Presence Of Harmonic Distortion

Proceedings of the 5th International Conference on Harmonics in Power Systems (ICHPS V), 345–351.

Optimal Throughput and Energy Efficiency for Wireless Sensor Networks: Multiple Access and Multipacket Reception

EURASIP Journal on Wireless Communications and Networking, 2005(4), 670575.

A portable near infrared spectroscopy system for bedside monitoring of newborn brain

BioMedical Engineering OnLine, 4(29).

Modeling and Control of an SOFC APU

(No. PNNL-15396). Richland, Washington: Pacific Northwest National Laboratory.

Exchange Effects on Electronic States in QWs with e-h Plasma in an Electric Field

AIP Conference Proceedings, 772, 1234–1235,

L-valley electrons in SiGe heterostructures: highly anisotropic and tunable Zeeman and Rashba-like spin splittings

AIP Conference Proceedings, 772, 411–412,

Analysis of the Δ(X) − L intervalley mixing in group-IV heterostructures

AIP Conference Proceedings, 772, 409–410,

Thermoelectric power factor in semiconductors with buried epitaxial semimetallic nanoparticles

Applied Physics Letters, 87(11), 112102.

Fabrication of wafer-scale, aligned Sub-25 nm nanowires and templates using Planar Edge Defined Alternate Layer (PEDAL) Process

Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show. Presented at the 2005 NSTI Nanotechnology Conference and Trade Show, Anaheim, CA.

3Gb/s AC-coupled chip-to-chip communication using a low-swing pulse receiver

Proceedings of the 2005 International Solid State Circuits Conference. Presented at the 2005 International Solid State Circuits Conference, San Francisco, CA, USA.

An integrated self-masking technique for providing low-loss metallized RF MEMS devices in a polysilicon only MEMS process

Proceedings of the SPIE Micro Europe. Presented at the SPIE Micro Europe, Sevilla, Spain.

2.8 Gbps inductively coupled interconnect for 3D ICs

Proceedings of the 2005 symposium on VLSI circuits, 352–355.

Impact of SOI research Project on microelectronics education: a case study

Proceedings of the IEEE International Conference on Microelectronics systems education, 33–34.

Parallel computing environments and methods for power distribution system simulation

In 2005 Ieee Power Engineering Society General Meeting, Vols, 1-3 (pp. 215–220).

Modeling uncertainties in aggregated thermostatically controlled loads using a state queueing model

In 2005 Ieee Power Engineering Society General Meeting, Vols, 1-3 (p. 1336).

Modeling uncertainties in aggregated thermostatically controlled loads using a state queueing model

Ieee Transactions on Power Systems, 20(2), 725–733.