Electrical & Computer Engineering

Automated Architectural Exploration for Signal Processing Algorithms

In 2006 IEEE Workshop on Signal Processing Systems Design and Implementation (pp. 274–279,).

Architecture for Energy Efficient Sphere Decoding

2006 IEEE International SOC Conference, 267–270.

Compact Electrothermal Modeling of an X-band MMIC

2006 IEEE MTT-S International Microwave Symposium Digest, 651–654.

Performance Trend in Three-Dimensional Integrated Circuits

2006 International Interconnect Technology Conference, 45–47.

Exploring Compromises among Timing, Power and Temperature in Three-Dimensional Integrated Circuits

DAC '06: Proceedings of the 43rd annual Design Automation Conference, 997–1002.

Tool Integration for Signal Processing Architectural Exploration

Hourani, R., Jenkal, R., Davis, R., & Alexander, W. (2006, April). Presented at the Electronic Design Process (EDP) Workshop.

Breaking Rent’s Rule: Opportunities for 3D Interconnect Networks

VLSI Multilevel Interconnection (VMIC) Conference, 228–233.

Demystifying 3D ICs: The Pros and Cons of Going Vertical

Davis, W. R. (2006, April). Presented at the Virginia Tech ECE Department Seminar, Blacksburg, VA.

A Network based, Delay-tolerant, Integrated Navigation System for a differential drive UGV using Harmonic Potential Field

Proceedings of the 45th IEEE Conference on Decision and Control.

Aluminum-Based High-Temperature (>200°C) Packaging for SiC Power Converters

Proceedings 2006 International Symposium on Microelectronics : October 8-12, 2006 : San Diego Convention Center, San Diego, Calif., 734–741. Washington, D.C.: IMAPS.

High-temperature, high-density packaging of a 60kW converter for >200/spl deg/C embedded operation

High-temperature, high-density packaging of a 60kW converter for >200/spl deg/C embedded operation. Twenty-First Annual IEEE Applied Power Electronics Conference and Exposition, 2006. APEC '06. Presented at the Twenty-First Annual IEEE Applied Power Electronics Conference and Exposition, 2006. APEC '06., Dallas, TX.

Experimental Study of Thermomigration in Lead-Free Nanoelectronics Solder Joints

Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology. Presented at the ASME 2006 International Mechanical Engineering Congress and Exposition.

Experimental Damage Mechanics of Micro/Power Electronics Solder Joints under Electric Current Stresses

International Journal of Damage Mechanics, 15(1), 41–67.

System and method for non-uniform cache in a multi-core processor

Hughes, C., Tuck, J., Lee, V., & Chen, Y.-kuang. (2006, June).

Boosting SMT trace processors performance with data cache misssensitive thread scheduling mechanism

Microprocessors and Microsystems, 30(5), 225–233.

Energy-efficient thread-level speculation

IEEE Micro, 26(1), 80–91.

Bulk disambiguation of speculative threads in multiprocessors

ACM SIGARCH Computer Architecture News, 34(2), 227–238.

Are we ready for high memorylevel parallelism?

4th Workshop on Memory Performance Issues.

Locality-based Information Redundancy for Processor Reliability

2nd Workshop on Architectural Reliability (WAR-2) held in conjunction with 39th International Symposium on Microarchitecture (MICRO-39), 29–36.

PMPM: Prediction by Combining Multiple Partial Matches

2nd Championship Branch Prediction (CBP-2) held with the 39th International Symposium on Microarchitecture (MICRO-39), 19–24.